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B4 Thinker - 4 bit homebrewed computer

Scratch built architecture of a CPU and some of its peripherals.

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About 10 years ago, I challenged myself with this. What if the entire knowledge of how to build a computer or a microcontroller would suddenly disappear? Would I be able to build a simple MCU architecture from scratch? I mean, most of the HW developers these days are able to draw the schematic of a logical gate using BJT or MOSFET transistors. People are usually able to make the transition from simple semiconductor components to logical gate structures. How about 2 or 3 levels up for creating an entire ALU architecture or even further: an entire CPU?

Back in 2014 when I drew the first schematics of this architecture, my initial goal was to see If I can do it. After a while I wanted to take it one step further and actually build this as a modular design. Wouldn't it be nice if I could have like a motherboard with several modules connected to it? And then have at least a port card with 8 LEDs connected on top of it? in this way I could actually write a simple assembly program to work out at least a dynamic light loop with a bitwise shift instruction or something.  

Essentially, this ends up being nothing else than a simple microcontroller structure with most of the submodules that anyone can find in any $2 microcontroller. But the exercise itself and the gained knowledge is priceless. The current project features full STEP BY STEP in word explanations and detailed description of what happens each step of the way in this machine, thus making it a great source for learning. 

The presentation of this project starts with the instruction set table. 

The green marked fields are the instruction modules that I already implemented in hardware. They should work, regardless the fact that some other modules are not finished yet. This is the beauty of having a modular design. Even if this architecture is not final yet, it should still run code that use the available instructions. 

Each instruction takes 4 clock pulses to complete and then most of the blocks reset to their default state awaiting for the next cycle. The execution of the entire cycle is based on activating four different lines for each of the four pulses. Each specific line does something different for each individual module and for more information you would have to check the Instructions section of this page. 

Main architecture of what could become the motherboard:

Open in a new window for zooming in more accurately. As you can see, the circuit is a modular one and it is supposed to work even if, at some point, some instruction modules are missing. Moreover, my plan was to slowly improve the schematic by working some of the modules on breadboard. A modular design in this case, also allows for temporary replacing some of the cards with universal arduino launchpads which can temporarily perform the function of that specific module until it is finished. At first, in the testing phase, the clock generator module would have to be set to very slow speed or even manual pulses for better ability of diagnosing the circuit.   

Main characteristics:

  • 255 lines x16 bit Flash - (PC can go from 1 to 255 and the ASM code can only be this long)
  • 255 Bytes of RAM
  • 1 Byte output port, found at the FF RAM location
  • 4 clock pulses per instruction cycle
  • 10KHz max CPU frequency 

Credit and inspiration:

This design is 100% my brain work. However, the university years when I studied the Z80 uP and the vast experience I have with ASM programming and studying the datasheets of PIC Microcontrollers, inevitably added certain flavors to it. 

Disclaimers:

- This particular project aims to be a proof of concept. Right now it is not fully tested and debugged. I noticed that some of the submodules could be optimized. Although I plan on updating and fixing this design in the future, I cannot guarantee that the whole assembly is fully functional. 

- This project is only in a draft stage right now. Some of the parallel instruction modules are missing from the main schematic for the sake of keeping it as simple as possible for others. 

- The purpose of this project is also to pass on information to other interested people out there and teach others. So this project does not aim to be a DIY project that can be replicated and work flawlessly out of the first trial. 

- My dream would be that, at some point, I could prototype this computer and play with it in real life. Stay tuned and follow this project if you want to be notified when I add more info.

B4_thinker_AND_OR_block_Schematic variant.dch

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dch - 362.03 kB - 08/14/2024 at 06:35

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B4_thinker_E_block.dch

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B4_thinker_300_ROM-PC_Block.dch

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B4_thinker_INCAC_DECAC_block.dch

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dch - 262.51 kB - 08/14/2024 at 06:35

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B4_thinker_400_Instruction_decoder_Block.dch

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View all 17 files

  • 1
    0000 NOP instruction detailed description

    0.Initial state

    -the data bus is selected on read mode to all the blocks and the bus lines are LO
    -the SIO are in undefined states
    -The exec pulse is not present

    1.M_clk1 (PC pulse) increments the PC counter and modifies the address of the ROM to the new line
     -the memory puts the NOP (0000) on the instruction bus and the afferent data word (XXXXXXXX) on the data bus
     -the instruction decoder enables the line no 1
     -line 1 is not connected
    2.M_clk2 -
    3.M_clk3 (Exec pulse) does nothing because all the logical AND gates having this line as an input, are having the other lines LO
    4.M_clk4 deactivates (by reset) the R/W lines and all the blocks on the bus are in read mode.

  • 2
    0001 LTAC

    0.Initial state

    -the data bus is selected on read mode to all the blocks and the bus lines are LO
    -the SIO are in undefined states
    -The exec pulses are not present

    1.M_clk1 (PC pulse) increments the PC counter and modifies the address of the ROM to the new line
     -the memory puts the LTAC (0001) on the instruction bus and the afferent data word on the data bus before the I/O buffer of the 300 Block
     -the instruction decoder enables the line no 2 of the SIO
     -line 2 activates two logical and gates at the Enable of the I/O buffer at the output of the Block 300 and at the Enable of the I/O buffer junction
     -line 2 also goes into an AND logical gate connected on the parallel load of the AC
    2.M_clk2 swithces the I/O junction buffer and the block 300 I/O buffer on through the logical AND gates
    3.M_clk3 (Exec pulse)enables the parallel load on AC opening the AND gate
    4.M_clk4 deactivates (by reset) the I/O buffer lines and all the blocks on the bus are in read mode.
     -this pulse also switches off the I/O junction buffer

  • 3
    0100 INCAC and 0101 DECAC blocks

    0.Initial state

    -the data bus is selected on read mode to all the blocks and the bus lines are LO
    -the SIO are in undefined states
    -The exec pulse is not present

    1.M_clk1 (PC pulse) increments the PC counter and modifies the address of the ROM to the new line
     -the memory puts the INCAC (0100) on the instruction bus
     -the instruction decoder enables the line no 5
     -the junction buffer before the AC and the I/O buffer at block 300 are deactivated by default
    2.M_clk2 (Exec pulse) puts the increment pulse on the AC register and opens the I/O output buffer of the Carry flag
     -the AC increments
     -if the CO output of the AC gives a pulse, the Carry I/O buffer will latch HI
    3.M_clk3 (Exec pulse) enables the parallel load on the FLAGS register and this will store the C or Z present flags
    4.M_clk4 deactivates (by reset) the I/O buffers and all the blocks on the bus are in read mode. 

    0.Initial state

    -the data bus is selected on read mode to all the blocks and the bus lines are LO
    -the SIO are in undefined states
    -The exec pulse is not present

    1.M_clk1 (PC pulse) increments the PC counter and modifies the address of the ROM to the new line
     -the memory puts the DECAC (0101) on the instruction bus
     -the instruction decoder enables the line no 6
     -the junction buffer before the AC and the I/O buffer at block 300 are deactivated by default
    2.M_clk2 (Exec pulse) puts the decrement pulse on the AC register and opens the I/O output buffer of the Carry flag
     -the AC decrements
     -if the BO output of the AC gives a pulse, the Carry I/O buffer will latch HI
    3.M_clk3 (Exec pulse) enables the parallel load on the FLAGS register and this will store the C or Z present flags
    4.M_clk4 deactivates (by reset) the I/O buffers and all the blocks on the bus are in read mode. 

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lohikarhu wrote 09/01/2024 at 19:01 point

Quite the build, and interesting design... My first understanding of what "software" is, came from learning the cycle by cycle operation of a PDP-11/05, at the gate level... "Oh, software is just reconfiguring hardware, a step at a time!"

Just what you are doing!

Nice!

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