The problem

This turned out to be my biggest repair to date with 19 days of testing logged into my journal and many more spent reading the manual. From the moment I opened it's lid it was apparent that no clear cut solution like swapping dried out PSU caps was gonna get this old guy back in order.

The symptons are simple enough, the multimeter reads 0.00000 Volts regardless of what you plug at it's input or what type of measurement you perform, everything else behaves properly though: Display, firmware version at boot up, switches, etc. This points away from microprocessors, memory, peripherals, etc and suggests the A/D converter  might be at fault, thankfully though the owners manual is a gem from the past, the first 79 pages explain how to operate the machine, the following 236 explain how to repair it, you would never dream of such attention to detail nowadays, in fact if you are reading this looking for ways to repair yours I'd advise you to go look at the owners manual instead, you'll find most of what you need there, I will give advice on a couple of matters that you might find helpful though so consider rereading this once you've gone over the manual.

Not only the manual is prepared to thoroughly assist you in your troubleshooting but the machine is too, many test-points are generously layed out in all PCBs, a short-lived technique known as "Signature Analysis" is employed to troubleshoot digital circuits and most importantly a "Self Test" button in the front tells the microprocessor (μP from now on) to test various functionalities in your machine so that you can start troubleshooting, mine gave error at test 7 which does indeed suggests somethings wrong with the A/D converter.



ADC Theory of Operation

Before following with the troubleshooting attempts let's first summarize the principles of operation for this device. The basic concept behind it's ADC is the "Multi-slope II" technique, to understand it let's build up from the more ubiqutous "Dual slope" technique. This technique pictured on [Fig. 1] measures an input DC voltage by first charging an integrator cap for a fixed amount of time labelled integration in [Fig. 2] this process is what we call "runup", after that time has passed the μP starts counting again clock cycles and switches the input to a "Slope Generator" a precise current source that discharges the charge built up in the integrator cap at a known fixed rate thus dropping the voltage on the cap, finally a "Zero Crossing Comparator" signals the μP when the voltage has reached zero and it stops counting, this is what we call "rundown". 

One can understand the operating principle by looking at [Fig. 2], we are essentially comparing our known charging rate against the input charging rate. Another way to look at it is from the perspective of elementary school math, the problem is pythagorean in nature: "knowing the length of the bases and the slope for the right most triangle find the slope for the left most triangle".

                                                                               Fig. 1: Dual slope. Block diagram

                                                                   Fig. 2: Dual slope. Voltage over time at the integrator cap

This technique is no doubt smart since it makes use of the timing precision in digital electronics that is now ubiqutous everywhere, employing also a precise current source it is able to perform highly accurate measurements, however one can quickly see some problems appear: Say that we want to perform a higher voltage measurement, now the runup slope will be higher, the voltage at the integrator after runup will be higher too and thus we'll take longer to discharge it. Ideally we would like to measure at higher frequencies and not an ideal DC voltage. A few things can be done to improve this.

A first implementation would be to speed up during rundown, initially a higher current source could discharge the integrator to near zero, then we'd switch to a lower current source which would land it softly at zero to allow for a precise comparison. This is the basics for "Multi-Slope I" (pictured below).

                                                  Fig. 3:  Dual slope and "Multi-Slope I" comparator

This is already an improvement but the HP 3456A can do an even better job. To achieve a fast and precise result the Multi-Slope II employs up to 4 different current sources or "slopes" to calculate each of the last 4 significant digits on the measurement [Fig. 4]. Each slope (a decade smaller than the last) will be employed by the μP to steer the integrator voltage towards zero in successive approximations of higher precision at the cost of longer times. 

For instance, say that the input voltage was positive: To calculate the most significant of the 4 digits the μP first connects the integrator Cap to a big negative current source with slope -S4, this slope will quickly discharge the cap and reach a zero crossing, quickly but at a cost of low precision. After this slope overshoots zero for a fixed amount of time a different current source one decade slower +S3 will be connected to the cap to steer it towards zero once again, this will again reach zero and overshoot but the time it took to do so will give the μP information about the next least significant digit. This process is repeated for -S2 and +S1 until the last zero crossing. This way the ADC will quickly reach a measurement and calculate each digit throughout the measurement.

                                              Fig. 4: Rundown technique for the HP 3456A, the "Multi-Slope II"

Now, while we referred initially to 4 slopes it would be more accurate to refer to 4 pairs of positive and negative slopes, depending on whether the voltage was positive or negative the μP will need to employ a negative or positive slope respectively to steer towards zero, [Fig. 5] shows the case for either 10.00V or -10.00V where the first slope S4 has to be used in it's positive or negative form to reach zero.

                                                          Fig. 5: Multi-Slope II rundown for 10.00V and -10.00V

The HP 3456A ADC still has a final trick up it's sleeve though, you might've noticed only the rundown slopes are pictured in [Fig. 4], this is because the runup slopes can get complicated. In it's fastest mode (0.01 Power Line Cycles of integration time) the runup slopes looks just like the Dual-Slope or Multi-Slope I, however if one wanted to sacrifice speed (0.1 PLC and above) for resolution and uncork more digits a some of the most significant digits could be calculated during runup leaving the remaining 4 to be computed during rundown.

This is achieved by steering the integrator cap voltage towards zero with either +S4 and -S4 while the input voltage is still charging the capacitor, the reason might seem strange at first, I know it was to me, however I'm going to try to make sense of it here. I found it very helpful to compare how the μP will compute the most significant digit for both a high and a low input voltage. 

High input voltage MSD: First the capacitor is allowed to charge normally through the input voltage [Fig. 6], since it is high the voltage shoots up to a high level at a steep slope, now the μP begins steering towards zero by hooking up the -S4 slope generator to the input cap as well as the input voltage, the capacitor discharges but really slowly since the current source is barely over powering the big input voltage. Once a fixed period has passed the μP checks the polarity of the voltage with the comparator (the current source is momentarily disconnected at this time which explains the smaller steps) like in rundown if the polarity has not reverted the μP will hook up again an -S4 slope trying to steer towards zero. Eventually the slope will reach and overshoot zero though (not pictured) and the μP will try to steer towards it again but now by steering "upwards" with an +S4 slope, this, in conjunction with the big input voltage will shoot up the voltage once again arriving at a level close to where the cap was before steering and the process will start all over again. The μP takes count of how many -S4 and +S4 slopes where employed during runup, and one can easily see how a large positive input voltage would tally up to a high number of -S4 and a low number of +S4 slopes. A large negative input voltage will employ many +S4 slopes and only a few -S4. The Most Significant Digit will be inferred from this ratio

Low input voltage MSD: In this case [Fig. 6] the low input voltage will barely charge the capacitor at the beginning and when the first -S4 slope is added to the minuscule charging rate of the input voltage the rate is immediately overpowered by the current source and zero is reached and overshooted at the the first counts. The μP then sees that the polarity at the comparator has inverted and thus it steers towards zero, now with an +S4 slope, again this slope quickly overshoots and at the next evaluation step the μP switches slopes again, this is repeated over and over again oscillating around the zero line however one can see that the small effect of the input voltage charging rate is not completely negated, there is indeed an overall downwards trend to this oscillation and eventually (not pictured) there will come a point where the whole graph has drifted low enough that only one upwards +S4 slope will not be enough to reach zero and an additional subsequent +S4 will have to be employed to reach zero again. This means that at the end the rate of +S4 slopes to -S4 slopes will be slightly skewed towards +S4 but not by much, this like before is how the ADC realizes the MSD corresponds to a really small value (The exact calculation taking place at the firmware is not stated anywhere).

                                              Fig 6. Multi-Slope II runup for higher precision measurements

Troubleshooting Error 7 with decision tree

Now that we have gathered a general feeling for how the ADC operates we may face the troubleshooting, the manual gracefully features a "follow your own adventure" type of guide, it asks you to perform a certain test and then directs you to a different test depending on what the result for that test was, I followed through with the repairs and decided to log what I already tested in the following chart:

                                                                   Fig. 7: Test 7 Fail Decision Tree and my outputs

Fixing the voltage reference

This turned out to be a not so fruitful endeavor I think partly because the decision tree assumes there's only one thing failing in your machine and I later found out mine was suffering from two distinct failures caused in different sections. Most of the "Test 7 Fail" section calls for testing with a logic analyzer, for me it lead nowhere but I'll share a couple of tips in case anyone is in a similar position. I purchased a super cheap 8 channel "AZ delivery" logic analyzer (a Saleae clone). The machine is not great per se but paired with the open source software "Sigrok Pulseview" it can do wonders, specially with slow clock machines from the 90s. One of it's features is decoding signals with the "Signature" decoder, an HP protocol with only one purpose, to troubleshoot their lab gear, the probes are hooked to test points labeled start, stop and clock, the 4th probe is hooked to whatever digital line the user wishes to test for failures, the  user then will configure the equipment to a particular state, the string of bites between start and stop is decoded and "compressed" into one single code of 4 characters, this code can then be checked against the one specified in the manual. I like to think of this as an early form of CRC. [Fig. 8] shows an erroneous bit stream later identified as erratic because of coupled noise.

                                                                    Fig. 8: Logic Analyzer Output for an erratic bit stream

After much checking I decided to ignore the decision tree and go back to basics, I started checking voltages throughout the machine and found the voltage at the reference was severely off, the various buffered and inverted values were out of whack: 

-12Va REF

-15’4V

-12Vb REF

-15’43V

+12V REF

+13’99V

This is one of the errors one prays not to get when gambling on ebay on a precision DMM as there is no way to get the voltage reference back into spec without going through some costly calibration process involving precision references or sending it out for calibration. What follows is a block diagram overlay on top of the reference schematic, it may look daunting at first but it's nothing more than a heated Zener reference that provides a low accuracy high precision voltage followed by a non-inverting opamp that gets the stiff voltage to an accurate -12V by means of a series of proprietary laser trimmed resistors, these resistors can be shorted through jumpers to get the Va reference to match -12V during calibration. The rest of the schematic is simply a couple of buffers that probably protect the reference from switching noise in the rest of the circuit.

                                                                    Fig. 9: DMM reference schematic and Block Diagram overlay

The reference being off alone should not account for my DMMs symptoms, I would expect inaccurate readings but not a stable 0V at the screen, this pointed to a secondary problem in the ADC but for now I soldiered on with the reference. To me troubleshooting feedback loops is more complex than feedforward signal chains, in direct input to output chains one can test elements individualy backpropagating from ouput to input and find the point where the signal chain breaks, this strategy is not as applicable to feedback loops as the error is propagated back into the input. For example, one would be tempted to check whether the reference is busted reading it's output but the bias voltage for the reference is the -12V output itself, is the reference busted or is it receiving a bad bias voltage from another element on the loop? To get a feeling for the reference health I decided to check it's output voltage -6.98V and it's bias current by measuring the voltage drop in it's bias resistor and applying Ohms which gave 2.3mA, this value falls within spec in the V-I curve for the Zener [Fig. 10] which implies it could be okay but it's only being driven hard by some other component.

                                                                    Fig. 10: Zener reference I-V curve

Following that I moved to checking the U501 opamp which was putting out -16.25V and had a couple hundred mV drop between it's inverting and non-inverting inputs, (the opamp markings in my A3456-66525 reference board where not clear but I identified it as a OP07 from Analog Devices) the output being 2V away from the supply is another indicative of an old opamp saturating. After checking that the loop was indeed closed and that the resistors fixing the gain in the precision voltage divider at U500 had not drifted I checked the emitter follower buffering the opamps output. 

I then tested Q501 for shorts but it tested open and both it's fwd voltages looked fine, I moved to the protection diodes in the emitter follower stage, as I was applying some soft pressure to lift one leg of CR502 the body broke into two pieces, I then switched on the DMM and the reference voltages where much healthier! Also the broken diode is pretty easy to come by this days.

Sadly this means that the calibration has drifted quite a bit from -12,000000V to -12,04V which means I'll have to send it for calibration and the DMM still didn't work as it read OL on all measurements and threw a new Error 4 in self test. This proved that the ADC section was also at fault.

Fixing the Multislope ADC