That's the name so far, I'll have to check it's not already in use somewhere else...

But it's a decent working title.

No idea if I'll spin it off this main project, we'll see.

Previous works :
42. The "same" symbol
43. PAM3 and the bi-Trits
45. Constellation 2
59. MAC & PHYs
62. Sub-protocol: QSDE

The basic idea is the same : a pair of PAM3 signals per lane to transmit 3bits or one S symbol.

PAM3 uses only 2 comparators, or 4 FPGA pins for the analog/digital interface for each lane. 2 pins for transmission. Two lanes need (4+2)×2=12 pins.

The transmitter and receiver hold only a very limited quantity of data: 2 3-bit words, to detect repetitions. Some reclocking and clock domain crossing will happen as well, the scrambler must provide the required FIFO.

One digital clock symbol uses both edges to consume the whole 3-bit nibble:

• At 25MHz, that's 25×3=75Mbits per second, not bad.
• it can reach 90Mbits per second at 30MHz if the AFE is capable of it and the cable allows...

The 9 symbols have beeen defined in 45. Constellation 2:

The S symbol (Silent/Same) plays a crucial role since it can destroy synchronisation if used in a long sequence:

• A constant stream of S means loss of synchronisation, so the FSM returns to the Q state after about 8 or 16 consecutive occurrences. The PLL can be considered lost if no adjustment (+/- phase) has not occured during a given sampling period.
• One S can appear after another data symbol to indicate repetition (hence the "Same" name). This reduces the odds of droop and high frequency EMI. Its chance of appearing is 1/8 for a random stream, it's not enormous but not insignificant.
• A repeating pattern of data that does not use the "S" symbol represents a synchronisation pattern => the receiver goes to state Sync when the PLL is locked. The pattern can change to indicate that the local PLL is locked and the peer can start sending data.

Obviously, to bring the link up, the receiver and transmitter of each peer must exchange data, to send the proper sync burst (locked or not). This can take a good number of cycles, not yet limited. This negotiation takes place at the beginning, to establish a link, so it's not an added latency at the start of each transaction.

Detection of line polarity takes place there, using the 110 and 111 symbols to determine whether + or - comes first. To help in case a peer gets connected in the middle of a sync burst, the bursts are short (8 ?) and separated by one S.

When lock is achieved, the synch pattern can switch to ++/-- (pairs of 010 and 011), which is 4× lower frequency but still enough transitions to keep the PLL locked.

Transition to transmission of data requires one other symbol to terminate the string of ++/--. Since the data could start with any value, a single S symbol is the only one that works, since data must start by a non-S symbol. Thus the 0 level will indicate the transition to data mode, and at most 3× consecutive 0 levels will be transmitted, with no risk of PLL loss.

This sounds reasonable, maybe not the most efficient, but still good enough for Cat5 at 10-30MHz.

The "Same" protocol (preventing repeats of identical symbols) makes sure that a given level does not last more than 2 bauds. Short term droop is reduced but long-term baseline wander is another beast though.

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OK the protocol should be called QSLDE instead :

Quiet / Sync / Locked / Data / error (which is in fact Q, as well, so it can be discarded and we get QSLD.