The latest developments have seriously affected the pipeline, here is the new version:

A lot of details have been shoved and hidden in the 63. miniPHY circuits so it looks simpler than it really is. But hopefully this modularisation will help the project move forward.

A new stage has appeared to slice the 20-bit word into smaller nibbles, here I have chosen the width of 3 bits. This means one more development "but it should be simple" right ? Considering it's where data cross a clock domain, we'll see...

GrayPar is mostly unaffected. But the PEAC16x2 is changed to gPEAC17 for 2 reasons:

1. the C/D signal is now part of the payload so data words are now 17 bits,
2. error cascading means the gPEAC modulus must have its 7 MSB cleared.

The pipeline also features a "quarantine FIFO" used to validate the NOP control words.

GrayPar needs modifications to adapt for the new data layout: the C/D signal must be mixed with the 16 bits of data, the control counters are now gone. The comparison is reduced to m0/m1 at this point, and moved after the receiver's gPEAC.

This means that GrayPar has a main part with 17 signals (d0-d15 and C/D) that alter m1/m2, which are expanded to 3 signals with the parity. Thus the whole layer must be re-rebuilt.