The new diagram is here:

It's not changed but more precise, since the bus widths were not clear enough.

• X contains 19 bits, as it is a concatenation of the 18 data bits (fitting the modulus) and the carry bit.
• The adder is 18+18+1 bits, outputting 19 bits (including carry out).

Another "trick" is that the carry bit from X does not need to be ANDed with the phase since it MUST be 0 at the end of phase 0. It can only be 1 at phase 1. (That change is not yet applied to the Y path)

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Yeah, forget that, I messed up again. The ANDN must be restored...

There is something else to consider : the carry !

The adder is 18-bit wide, and unlike the C code, it truncates the input such that the 2nd cycle does not propagate or keep the carry out of phase 0. Actually, the carry should be "sticky" (ORed) during the phase 1.

This is not represented here, and although putting everything in the X / Y registers simplified the overall algorithm, it confuses the schematic and RTL code. The next revision should address this.