Today we finally sat down and tested the Signal-Logic chip, the chip responsible for creating the RW and WR signals and also some other signals like the MEM_RD/MEM_WR that is used for the banking system.

We have tried to validate this chip several times and did not get the correct functionality, on the contrary, we get the opposite functionality! Hmmm... When we expect a logical HIGH we got a LOW and vice versa. We even made a super simple 2 input and 2 output program to test but to no avail.

After several attempts of testing and reading we finally got it to work as assumed (don't ask how we fixed it, it was magic...). So now we have all 3 logic chip working as intended and tested. So next step will be testing the new bus transceivers to make sure we don't fry our processor. And when that is done, we can start test ROM & RAM. 

Name     Test ;
PartNo   00 ;
Date     2025-03-29 ;
Revision 1 ;
Designer Engineer ;
Company  Sperly Retro Electronics ;
Assembly None ;
Location  ;
Device   G16V8A ;

/* *************** INPUT PINS *********************/
PIN 2    =  A                         ; 
PIN 3    =  B                         ; 

/* *************** OUTPUT PINS *********************/
PIN 18    = Y                      ;
PIN 19    = X                      ; 

/* ********************* LOGIC *********************/
X = A & B;
Y = A # B;

This test program gave us inverted outputs and I did not figure out why.