So yesterday me and my son sat down and pulled out the logic analyzer to finally find the fault. First we used the oscilloscope to verify the power delivery, and it was rock solid. Then we hooked up the major part of the bus (on the peripheral side of the bus transceivers) and started logging...

Well what do you know, when we started to verify the code with what we measured we found 2 things that will destroy any chances of stable execution:

1. We found that when we loaded the stack pointer we used the wrong addressing mode, in the code we had "lds $E000" while it should be "lds #$E000". DOH! That meant we were loading the stack with an un-initialized value found at $E000 instead of loading it with actual E000. 
2. We also found small artifacts, only 5-15ns long, that in certain conditions made the processor more or less halt or reset. These spikes only appeared during write instructions, which lead me to believe that it could be a reflection or a spike from changing direction on the bus transceivers. 

So this artifact problem rushes the issue of adding pullups on the bus, which I already had planned for stage 3, but I need to add those pesky pullups on the BA, BS and R/W signals as well since I could see the blips there to. 

Hopefully this will make the bus a bit more stable and well behaved. 

TL;DR The Stage 3 is soon being ordered!