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Speed of current version

A project log for 3niti alpha

Ternary computer "3niti alpha" that I started to design in 2004

SHAOSSHAOS 06/13/2018 at 02:420 Comments

Current version of firmware of 3niti alpha simu1 simulates only TWO 27-triad pages - one in RAM (in PIC's data registers) and one in ROM (in PIC's EEPROM). I found my notes with approximate speed of each instruction, measured in 2011 (in microseconds):

        from RAM from ROM
NNN (SAN)     21       28
NNO (SAO)     21       28
NNP (SAP)     21       28
NON (SAF)     18       25
NOO (SPCD)    23       30
NOP (SAB)     18       25
NPN (SAL)     22       29
NPO (SAM)     22       29
NPP (SAH)     22       29
ONN (RLA)     23       32
ONO (ADD)     45       52
ONP (RRA)     23       32
OON (LAI #)   27       41
OOO (ADI #)   55       69
OOP (OPA #)   44       58
OPN (LDI ###) 48       76
OPO (JMP ###) 55       83
OPP (OPB ###) 93      121
PNN (LAN)     22 29*   29 36*
PNO (LAO)     22 29*   29 36*
PNP (LAP)     22 29*   29 36*
PON (LAF)     19       26
POO (LPCD)    24       31
POP (LAB)     19       26
PPN (LAL)     23       30
PPO (LAM)     23       30
PPP (LAH)     23       30
where * means with reading data from ROM

So for example LAF (load A from F) takes 19us (nineteen microseconds) if executed from RAM (52,631 times per second) and 26us (twenty six microseconds) if executed from ROM (38,461 times per second). 

When I add external I2C memory support with page caching in the PIC the speeds above (RAM column) will be true only if execution keeps running in the same page - to jump to other page firmware will need to read 27 triads from external memory and cache into RAM again...

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