The goal of this project was to design a simple 8bit asynchronous processor at the transistor level. The processor featured 4 instructions, one working register, and 64 bytes of shared program/data memory. Two programs were written for verification, a Fibonacci number calculator, and a Euclid GCD method.
Considering that I'm most familiar with logic design at the gate level, the most intuitive first step was to design logic at the transistor level, then design necessary chip logic at the gate level. This way, I could derive any chip logic at the transistor level by substitution.
Given that I wanted a processor, I came up with a simple instruction set: ADD, NAND, STORE, and JUMP NO CARRY (JNC). Four instructions yields two bit op codes, leaving me a 6 bit address bus, hence the 64 byte memory.
I did cheat on the clock a little bit. In the interest of time, I started with a 555 square generator whose width can be varied by a potentiometer. Past that, JK FlipFlops converted a quadrature wave, where all of the processor's combinational logic was generated on the leading rising edge, and latches trigger on the trailing rising edge, to account for propagation delay in the combinational logic.
The control logic was the most complicated part and contained two registers, the Instruction Pointer and the Instruction Register. The whole processor operated on a load/execute cycle. First, the byte stored at the instruction pointer's position in memory was loaded into the instruction register. Second, the instruction register's instruction was executed. LatherRinseRepeat. The control logic was the last thing I designed, after determining what signals needed to be generated for the other segments. The only operation that bypassed the ALU was JNC, which sets the instruction pointer equal to a literal, the bottom 6 bits of the instruction. Reset sets the IP to 0.
Lastly, the ALU. This was probably the most fun part to make. The ALU consisted of an ADD unit with carry, a bitwise NAND unit, and a set of 2:1 muxes to feed the output I cared about (based on the op code) to the accumulator register.