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• Walkthrough of the front-end design

  haas • 12/01/2024 at 20:07 • 0 comments

  When you hear "2 GHz oscilloscope", you might rightly wonder what kind of analog wizardry can possibly achieve such crazy bandwidth. Well, as you'll see, there was some care involved, but the real key was just to use some incredible components. In particular, the LMH5401 is a preamplifier with 8 GHz of gain bandwidth product that somehow only costs ~$10. We use it as a 4x gain, single-ended to differential amplifier. Then following that is the LMH6401, a 4.5 GHz bandwidth variable gain amplifier that somehow only costs ~$15. We use it to vary the gain by an extra factor of between -6 to 26 dB (~0.5x to ~20x), in 32 steps. Just using those two components, we basically have a 2 GHz front-end. The rest is just bells and whistles. 

  The front-end is basically all 50 Ohm (or 100 Ohm differential) impedance. 1M Ohm input impedance is accepted, but, as you'll see below, it is immediately turned into a 50 Ohm signal and then handled just like a 50 Ohm input.

  Let's take a look at the schematics. The first page is the "pre-input" part. A single-ended BNC signal comes in, and a 50 Ohm single-ended signal comes out, which will go to the LMH5401 preamplifier on the next page. Along the way, we are handling the splitting out of an analog input for oversampling, switchable 50/1M Ohm impedance, switchable 5x attenuation to increase the dynamic range, and AC/DC input coupling. The main goal here is to accomplish these functions without ruining the 2 GHz bandwidth before we get to the fancy preamplifier on the next page.

  We do have to be careful about the BNC input itself. Connectors are easy places to destroy bandwidth. Some BNC connectors only have 500 MHz or 1 GHz of bandwidth! We use Molex 73100-0105 BNC connectors, rated to 2 GHz, but I've tested them to 3 GHz and they show minimal losses (<1 dB).

  Next is a stage which can optionally split out half the signal to an SMA output on the front, so you can send it to a second Haasoscope Pro for oversampling. This is only on channel 1, since if you're bothering to oversample the signal, you're going to be using the ADC in single channel mode to first get the full 3.2 GS/s for the channel. The splitting is done by a simple resistive divider in the Delta configuration. It maintains the 50 Ohm impedance of the signal along both paths. We're assuming that the signal is 50 Ohm here, because only 50 Ohm has 2 GHz bandwidth and would require oversampling. Half of the signal is lost to heat, but that's OK, we have amplifiers afterwards. 

  This, and other options, are switched on or off by a relay. But not just any relay - most will only have a few hundred MHz of bandwidth. We need special "RF relays". Here I settled on the Omron G6K-2F-RF-T, which is rated to 3 GHz, but really starts to degrade significantly after 2 GHz. But that's good enough for us here, and already it's ~$10 each. Better relays are available, but can easily be ~$100 each! They're DPDT relays, so it's easy to route signals either on one path or another path, since there's an "input" and an "output" switched simultaneously. If the relay is off, the signal just goes straight through on a 50 Ohm wire to the output. If the relay is on, the signal goes into the splitter and half of it goes to the output.

  The next stage allows for switching to accepting 1M Ohm input impedance, for using standard 10x passive probes. These probes inherently don't have large bandwidth - the ones I usually use, the Rigol PVP2350 have 350 MHz of bandwidth, and the most you're likely to get from any passive probe is about 500 MHz. This is far from 2 GHz, so why bother with 1M Ohm impedance at all? Well, for one, some people just like to use 10x passive probes and don't care about the bandwidth. Second, if we're in two channel mode for the ADC, we have 1.6 GS/s per channel, and that's not such overkill for 500 or even 350 MHz of bandwidth.

  The goal here is to deal with 1M Ohm input impedance, but then immediately turn...

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• Early Development

  haas • 11/28/2024 at 04:59 • 0 comments

  In July 2024, the kids were off to camp, and I was off from teaching for the summer. Relax? Vacation? No! Work day and night developing my own 2 GHz oscilloscope! 

  The first goal was just to talk to the ADC chip and get it to do something. This would convince me I could solder the BGA chip correctly in my little reflow oven reliably, power the chip correctly, and let me start playing around with it. I had to connect an FPGA to it, to talk to it over SPI and receive the LVDS signals it sends out containing the ADC data. So I wired it up to an FPGA dev board that I had experience using, based on a Cyclone IV FPGA. You can see in the pic below all the 2mm spaced pins where the dev board would connect to this new board hosting the ADC chip on the left. There were also SMA inputs for the (differential) clock signal and two analog input channels to the ADC. I also added lots of debug headers so I could probe every signal going into and out of the ADC, plus debug the power and signals from the FPGA. There's also two headers on the right for connecting a module based on the FTDI FT232H chip I had experience with for interfacing the FPGA to USB2. 

  This is what the board looked like assembled, with everything attached to it. For power I was using these handy little USB-powered power supplies I found on Amazon to supply the ADC with 1.1V, 1.9V, and another 1.9V (separate for LVDS). The ADC also needs a very fast clock to tell it when to sample, 1.6 GHz. For this I used a cheap ADF4350 board from Amazon. But annoyingly it only had single-ended SMA output, whereas the ADC needed a differential output to two SMAs, so I used a cheap eBay single ended to differential converter. I also used another of these (not shown in pic) to input signals to the differential analog inputs of the ADC from my single-ended signal generator. To sync the clock between the FPGA and the ADF4350 board, I output a 50 MHz clock from the FPGA (big BNC connector sticking up) and connected it over to the reference clock input of the ADF4350 board.

  A lot of things worked! I could talk to the ADC chip over SPI just fine, reading back it's Vendor ID and serial number, setting its registers, and power it up and down. It could also see the clock from the ADF4350, and I'd see data coming over the LVDS lines into the FPGA. Below you can see the binary LVDS data coming in, when I'm sending in a 10 MHz or so pulse to the ADC analog input - I do see the bits going from 0 to 1 in unison on most of the LVDS outputs! It didn't work fast, only up to about 200 MHz, because those LVDS lines were hideous - very different lengths, going through tons of vias and even 2mm pin headers and who knows what on the dev board, and even unterminated. But it was more than enough to encourage me to move forward with the project.

  The next major step was clearly to put the ADC and the FPGA on the same board, and do the LVDS connections properly. 

  A very important lesson I'd learned, the hard way, was to break large projects into as many small blocks as possible. Especially for large hardware projects like this one, you don't want to put everything on one board at first. Start with each block on its own little board. Then it's quick, easy, and cheap to iterate versions of each little board you're working on, without redoing the other boards that already work fine.

  So I first made just a board with the FPGA on it, to get that working on its own. You can see a render of it below. It didn't really do anything except prove I could power it, program it with firmware over JTAG, see a 50 MHz clock input from the crystal, and make some LEDs blink. I also fanned out to .1" headers all the IO's, in case that would even be useful to me or others.

  The board worked just fine, first try!

  So then I was ready to make a board with an ADC and an FPGA on it, basically by merging together the first ADC board and the new FPGA board. ...

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• How it began

  haas • 11/22/2024 at 19:16 • 0 comments

  The original haasoscope was great, and still is, but as time has passed (6 years!) there were many ways I thought of to improve it.

  As I advanced in the kinds of projects I worked on, including high speed data acquisition for experiments at CERN, and one of the world's fastest random number generators, I found myself needing a much faster scope. I managed to get one, because I'm spoiled and have a great research budget, but I was shocked at how expensive they are. Even a probe was $1000+, at the low end!
  I started investigating why this stuff was so pricey. What I found was

  1. The market for fast scopes is smaller, so companies need to charge more per unit in order to recoup their upfront R&D costs
  2. They charge more because they can! A lot of the high end scope market is made up of companies and institutions, for whom money at the $20-50k level is not an issue

  I dreamed of one day making my own fast scope, to finally allow "ordinary people" to tinker with high speed electronics.
  I was inspired earlier in 2024 by an open-source 2 GHz active scope probe on hackaday. I printed and assembled a few of my own, and they worked great, for under $100 each! The probe was already half the challenge (standard x10 passive probes are limited to under a few hundred MHz) - now I just needed a fast, affordable USB scope.

  I did some research and initially hit some roadblocks. Most fast ADCs sent data out on high-speed serial links (12.5 Gbps+), which would require a "high-end" FPGA. Those can easily be many hundreds if not thousands of dollars, plus licensing fees for the software and IP, not to mention having to deal with assembling a 0.4mm pitch 782 pin BGA! I was entering a world of pain.

  But I then found a TI chip, strangely affordable, that also had a parallel LVDS interface. I could then use a "low end" FPGA - there are plenty of them with 100+ LVDS pairs for under $100, and free software and no licensing. I still had to deal with a 256 pin 0.8mm pitch BGA and a 484 pin 1mm pitch BGA, and routing ~80 LVDS pairs, each running at 800+ Mbps, but it finally sounded doable in principle.

  The routing was tough. At first I couldn't find a way to get all those signals out with less than 12 layers, and blind vias (as recommended in the data sheet / evaluation board layout). I priced it out and getting those made would be at least $500 /board in small quantities. (Blind vias are vias that connect only two specific layers of a multi-layer PCB, rather than holes going all the way through the board. They let you route other signals under (or over) the blind via, rather than having to go around it.) But I finally had a breakthrough and realized I could just get it to work, with only 10 layers, and no blind vias. I just needed thinner traces, 0.08mm (that's 80 microns wide!), and smaller vias, 0.2mm, directly under the BGA pads. Turns out that's just pushing the limits of some of the inexpensive Chinese PCB fabs, but they can do it! The boards can now be done for under $50 each in smallish quantities.

  The last obstacle was dealing with those BGAs. The FPGA could be assembled overseas, but the ADC was not available in China. I priced out having a US assembler attach the BGA, and we were back close to $500 again. I wasn't going to pay that, especially for some prototypes, of which I'd likely need many iterations. Wait, could I assemble it myself?! I bought a reflow oven on Amazon for $300 and watched some YouTube videos. It didn't look that hard. After practicing with some cheaper chips, I finally tried attaching the ADC to my board. It worked! And the Haasoscope Pro was born.

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