I went looking on some junk boxes while I am still waiting for parts and found these -
That's 104 Xilinx XC9536XL - 5 Volt tolerant 36 macro 10ns CPLD's.
I have ordered some level translators because I want a mix of 3.3 Volt chips and older 5 Volt chips like original CPU's.
I want the bus (backplane) to be 3.3 Volt LVTTL and not necessarily 5 Volt tolerant.
To achieve that I was going to use level translators for boards that had 5 Volt chips.
The translators I ordered are 9ns propagation delay data to data 10ns Output Enable (EO) to Data.
These CPLDs are 10 ns any pin to any pin so I might use them instead. This will also enable me to use the CPLD to rout signals making it easier to use single sided board.
Part of me doesn't want to use so much CPLD because it makes repeatability harder for others but I will use this as a starting point for flexibility.
If I use enough CPLDs (and I have 100 of them) the ordering of the signal on the backplane can simply be reprogrammed at a later time so that I don't have to commit to a signal bus layout to start with.
When I am more comfortable with a bus layout I will redesign using level translators instead of programmable logic at that later stage.
For now - looking at this -
I might just to a tidy up of the programming / design desk while I am waiting for the connectors.