This was a very fun project, my first attempt at a homebrew computer.
I mostly just followed datasheets and some great old books from the Uni library, mainly :
The design is very straightforward, the only tricky part is power-on reset generation as the 68000 requires the RESET_n and HALT_n signals to be held high for over 100 ms. This is accomplished with a 555 and open collector inverters, I have added the schematic for this part to the gallery.
Some glue logic is required to tie everything together, I used an Altera MAX 7064S because that is what I had, but the design fits in a 7032 as well.
I wrote the firmware in VHDL but I have included a RTL drawing in the gallery.