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Project RAD

8bit game console from an alternate reality

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8 bit game console that could have been designed in Japan circa 1986.

RAD86 is an old-school, tile-based 8 bit game console.

This project is all about FUN.

If we're not having fun, we're doing it wrong.

Capabilities fit somewhere between the Sega Master System and the PC Engine.

Target Specs :

  • Hitachi HD6309 CPU @ 3.6864MHz
  • 8KB General purpose Static RAM
  • 16KB BIOS ROM
  • 32KB Video Static RAM
  • 32KB-2048KB Cartridge ROM space
  • 4 controller support using Mega Drive 6 buttons controllers
  • Yamaha YM2203C 3 Channel, 4 operator FM + 3 channel PSG
  • Custom Video Display Processor

A reasonable effort has been made to select components that were available in Japan circa 1986 but suitable modern equivalents have been used when necessary.

By the represented time period, all consoles used custom Video Display Processors (VDP), so an off the shelf solution cannot be used. The MSX2 V9938 was considered, but the single 16 color palette was no fun, so we decided to make our own VDP.

Lacking access to a foundry we selected the Altera Flex10K10LC84-3 as our programmable chip to implement the VDP. This is a 1995 low-end 5V FPGA and is therefore anachronistic, but we stick to capabilities that are well within what was achievable in 1986 with gate arrays or ASICs of the period. As a small nod to modernity we use 2/3 of the internal RAM and 1/4 of the logic to implement a simple scan doubler and VGA controller.

That leaves us with 432 LUT and 256 bytes of Block RAM for the tile engine, sounds like fun!

VDP capabilities :

  • 32x30 8x8 tiles on a screen (256x240 pixels game resolution)
  • Integrated scan-doubler provides 640x480 60Hz output (512x480 visible)
  • Hardware-assisted horizontal and vertical scrolling
  • 4x 16 color palettes from a selection of 256 (RRGGGBBS encoding)
  • 64 8x8 sprites on-screen
  • 16 sprites max per scanline
  • 8bit control interface
  • 8bit SRAM memory interface
  • 9bit RGB output to a simple Resistor DAC

The current hardware platform, called the "DevKit" is the 3rd functional implementation of the design.

DevKit differs from the hypothetical "production" console by having sockets for extra RAM mapped to the CART ROM space. This RAMCART makes development easier than burning ROMs and swapping carts.

DevKit also includes a UART and built-in serial Monitor in ROM that is compatible with the NoICE debugger. 3x 20pin hardware debug headers compatible with Agilent logic analyzer termination adapters are also provided.

DevKit includes 32KB banked RAM instead of 8KB and uses a large 64KB BIOS ROM that can hold 2 FPGA bitfiles on top of the 16KB BIOS.

DevKit measures 170x170mm and is compatible with Mini-ITX PC cases.

RAD86_v3_Schematic.PDF

Current board revision schematic.

Adobe Portable Document Format - 1.32 MB - 05/09/2025 at 17:37

Preview

Layout.png

Board layout, 4 layer 170x170mm mini-ITX compatible

Portable Network Graphics (PNG) - 375.05 kB - 05/09/2025 at 17:36

Preview

  • 1 × HD63C09 8bit Microprocessor
  • 1 × YM2203C 3 channel FM Sound Chip with 3 channel PSG
  • 2 × R65C22 VIA Versatile Interface Adapter
  • 1 × EPF10K10 5V FPGA used as Video Display Processor
  • 1 × Mach211 5V CPLD used as Address Decoder and Memory Mapper

View all 7 components

  • VDP timing is good

    photondreams05/13/2025 at 17:47 0 comments

    Performed some measurements with the logic analyzer to see how close we were regarding rendering time.

    Game resolution on RAD is 256x240. Since composite monitors are getting less and less common, we upscale to 512x480 and add black bars on the sides to display on a VGA monitor.

    Render, upscale, display

    Our upscaling method is very simple. RAD has no framebuffer, rendering is done line by line to a pair of 256 bytes line buffers. One buffer is displayed while the other one is rendered to and we swap every second display line (every game line). We also display each horizontal pixel twice so each chunky game pixel corresponds to 4 small VGA pixels.

    First we render all background tiles to the line in order and then we check the sprite attributes and render those that are visible on the current line, up to our maximum of 16 sprites on a single line.

    Each line is displayed twice on the VGA port so we have a total of 63 microseconds to prepare the next game line.

    Timing analysis

    M1 marker indicates the end of background tile rendering which started on the first new_line pulse (M4 marker). Elapsed time for rendering the background tiles is 23 microseconds.

    M2 marker indicates the end of sprite rendering. In this test, there are 16 sprites visible on the line, which is our worst case scenario. Elapsed time for sprite rendering is 17 microseconds.

    At this point, render_state goes to WAIT for 23 more microseconds while we are displaying, but not rendering.

    Opportunities

    I am tempted to signal the end of line processing using the FIRQ line to the CPU.  At 3.6864MHz, 23 us translate to only 84 cpu cycles. It might just be enough to send a couple palette entries and allow for cool palette tricks.

    It's worth a try if I can find a tiny bit of space in the FPGA (currently using 576/576 LUTs).

  • YM2203 Soundchip test

    photondreams05/10/2025 at 17:29 0 comments

    As a test of the sound system here is a recording of the Space Harrier main theme, as arranged for the PC88.

    Straight from the console RCA output to the Scarlett soundcard.

    https://soundcloud.com/user-28436304/spaceharrier-ym2203-rad86

  • Schematic and layout images uploaded

    photondreams05/09/2025 at 17:45 0 comments

    I added the schematic for the current board revision.

    So far I know of 2 problems in this revision :

    1. I used the wrong footprint for my pcb-mounted buttons at the front and therefore I cannot mount them.

    2. My soft power-ON/OFF scheme only works when it is the only part of the board that is assembled. When everything else is mounted, power state just follows the state of the button. I make do with a jumper on the PW SW pins for now.


    I had made a cute little simulation of the circuit, but it did not survive contact with reality. I blame my very limited analog design skills.

  • Controllers working

    photondreams05/09/2025 at 17:34 0 comments

    Controllers 1 and 2, connected to VIA1 are now fully operational.


    I bought a few of these inexpensive Hyperkin GN6 controllers and so far I like them very much for the price.

  • VDP3 is complete

    photondreams05/03/2025 at 11:45 0 comments

    Got the VDP working with hardware scrolling in both directions.

    It's a tight fit but I am very happy!

View all 5 project logs

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