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Experimental Set Up

A project log for Compute In Memory in Ancient DRAM

Massively parallel operations in a 64kx1 DRAM from the 1980ies

timTim 05/05/2025 at 20:400 Comments

I will be experimenting with 4164 DRAMs chips which were used as main memory in many computers in the early 80ies. They are organized as 64k*1, so that eight chips are required for 64kbytes of RAM. Luckily I found a few from different vendors in my parts bin (I think I had more, but just kept one from each vendor.)

The 4164 required a single 5V supply. Their access times are rather slow, 200ns to 300ns for the devices I have. The generation rationale behind this experiment is that modern microcontrollers are vastily faster than these devices and can be used to generate timing violations required for compute-in-memory instead of having to use a FPGA.

I am going to use a CH32V003 microcontroller. These are rather low cost devices, but they come with 48MHz system clock and a RISC-V core (RV32EC), which as able to execute instructions 100-150x faster than a 1MHz 6502 from the 80ies. In addition, they offer 5V I/O which greatly simplifies interfacing to the 4164.

Some devices and the pinout are shown above. One rather nasty detail about these memory chips is that their supply connections are swapped compared to the standard TTL/CMOS corner layout. (Someone spent 2 hours debugging a magically self-heating chip...)

Wiring diagram and set up on breadboard shown below

| 4164 DRAM Pin | Function | CH32V003 Pin |
|---------------|----------|--------------|
| 1             | NC       | -            |
| 2             | DIN      | PD0          |
| 3             | W/R      | PD4          |
| 4             | RAS      | PD3          |
| 5-13          | A0-A7    | PC0-PC7      |
| 8             | VCC      | 5V supply    |
| 14            | DOUT     | PD5          |
| 15            | CAS      | PD2          |
| 16            | GND      | GND          |

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