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AEGIS: An Open Socketed ARMv9 Platform

Socketed ARMv9 CPUs, open LGA-Z1 socket, modular boards, and secure AI hardware for devs, builders, and infrastructure.

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What if ARM chips were socketed, open, and built for long-term ownership?
We’re building exactly that.

AEGIS is a new family of LGA-socketed ARMv9 processors and modular development boards designed for openness, repairability, and real-time system control. From dev kits to AI routers and infrastructure defense nodes, every layer is open and extensible — including the CPU socket.

AEGIS is a fully open, modular ARMv9 hardware platform — built to challenge the status quo of soldered-down, closed-source ARM systems. We’re developing a full stack of socketed ARMv9 CPUs, an open LGA socket standard (LGA-Z1), and development boards that anyone can extend, build on, or manufacture.

🧠 What We're Building

  • LGA-Socketed ARMv9 CPUs
    8-core to 128-core designs, optimized for modular computing, edge inference, and secure infrastructure.

  • Open LGA-Z1 Socket Spec
    Publicly documented. Meant to be adopted by third parties (ASUS, ASRock, etc.) for full ecosystem freedom.

  • Modular Motherboards
    DDR5, PCIe Gen4, NVMe boot, USB, Ethernet — available in dev kits, routers, and sensor node formats.

  • BIEM (Behavioral Integrity Enforcement Module)
    A PCIe coprocessor that enforces trusted execution, blocks unauthorized model or system behavior, and logs decisions.

  • Nova TPU
    A custom open inference engine supporting ONNX/INT8/FP16, deployable as a card in AI routers or edge nodes.

💡 Why This Matters

Most ARM platforms today are:

  • Soldered and locked-down

  • Lacking a modular upgrade path

  • Tied to cloud infrastructure or proprietary firmware

AEGIS changes that — we’re giving ARM the LGA socket it’s never had, with a roadmap that includes:

  • Developer kits

  • Open routers

  • Smart infrastructure nodes

  • Open hardware for AI and environmental protection

🛠️ Everything Will Be Open:

  • CPU mechanical specs + socket pinouts

  • Motherboard schematics

  • Expansion interfaces

  • Firmware hooks (LibreOS-compatible)

We welcome engineers, system builders, FOSS devs, and hardware enthusiasts to follow, fork, or help shape this open hardware platform.

  • AEGIS CPU + LGA-Z1 Socket: Help Needed for Layout, Validation, and Firmware

    Roy • 05/17/2025 at 15:07 • 0 comments

    Over the past few months, I’ve been developing AEGIS — an open hardware platform built around modular, socketed ARMv9 CPUs.

    AEGIS is an open, socketed ARMv9 platform designed to bring modular CPUs, developer-accessible dev kits, and secure AI enforcement to open hardware.

    I’ve now completed:

    • A full CPU roadmap: 8-core Hermes to 32-core Titan (ARMv9-A)

    • The open LGA-Z1 socket spec (targeting 1,100–2,200 pins based on CPU class)

    • Drafts for Libre Dev Kit schematics and board layout

    • Behavioral enforcement coprocessor (BIEM) + optional Nova TPU AI module

    This is an open-source hardware effort backed by provisional patents, public GitHub specs, and a commitment to full platform accessibility.

    I Need Help With:


    ✅ LGA-Z1 socket pad + footprint layout (KiCad or DXF)

    ✅ CPU-to-board signal integrity review

    ✅ DDR5 + PCIe Gen4 layout and simulation

    ✅ Platform firmware bring-up (coreboot, U-Boot for ARMv9)

    ✅ Spec formatting and open documentation review

    ✅ 2D/3D mechanical design for the socket + bracket

    This project is self-taught and driven by research, theory, and prototyping. I'm not an engineer by trade — just someone building open, secure hardware for developers and the future of AI and edge computing.

    If you’re passionate about CPUs, boards, open hardware, or firmware — and want to help shape something new — reach out. 🛠️

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Roy wrote 05/17/2025 at 12:15 • point

with what i am doing, I wont have to worry about it if i am not mistaken.  I am going to work on RISC-V as well.  

  Are you sure? yes | no

Donnie Agema wrote 05/17/2025 at 06:08 • point

With ARM increasing it's license fees, why not RISC-V instead?

  Are you sure? yes | no

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