These days, the ideas are

• combine the running sum with the error detection/correction bits
• borrow some design principles from TCM
• Implement the Viterbit-like decoder using an array of asynch gates, a sort of physical treillis
• move to 3 or 4 bits per sample instead of a simple 3-level input
• let the asynch gates treillis handle clock resynch

The size of the codes are still undetermined. The ratio could at worst be 1B1T, at best 3B2T or so.

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There is an "upper diagonal" (quite arbitrary where B=T, and a lower slop forced by 2^n >= 3^m.
If possible the words should be short to keep the circuit small but this reduces the encoding efficiency.

The remaining candidates are

• 1B1T : huh...
• 2B2T : like above.
• 3B2T : 9/8=1.125 => very little margin for ECC and no way to fight baseline wander
• 4B3T : 27/16=1,68 => first efficient BLW code but no room left for ECC
• 4B4T : 81/16=5.0625 => one added trit for ECC but the internal state is getting very large !
• 5B4T : 81/32=2.53125 => looks interesting, there is a bit more than 1 bit of extra data
• 5B5T : 243/32=7.59 looks overkill, almost 3 bits of added data

So how many bits do we need for both ECC and BLW? => this sets the ratio between B and T

And what could/should the ADC resolution be? => number of pins, 4 pins / 16 values looks like the maximum, but also 4 pairs makes a 5-value Flash ADC, that's 8 pins already...