Project description

The primary goal of this project is to create a standalone, paper‑programmable CPU that serves as an educational tool for teaching CPU architectures and assembly programming. At the same time, the CPU is sufficiently capable to support more sophisticated programs, which requires creative thinking to get the most out of the CPU's limited resources.

Achieving this calls for a careful balance between instruction set complexity and logic resource usage. On one hand, a reduced instruction set with a large memory allows complex routines through repeated simple operations (RISC approach). On the other hand, richer instructions can shrink program size when memory is limited (CISC approach). In a fully discrete implementation, both the number of logic chips and the size of program memory quickly balloon. By revisiting the TD4’s instruction encoding and overall architecture—eliminating wasted opcode bits and expanding operand flexibility—this design maximizes capability within a modest chip count and just 16 words of program memory.

Architecture

At its core, the CPU features four general‑purpose 4‑bit registers, doubling the TD4’s original count. Instructions are encoded in 6 bits: a 2‑bit opcode and 4 bits of operand/address data. Four primary operations are supported: immediate load into register X (LDX), register‑to‑register addition (ADD), conditional jumps on carry (JCC), and register moves (MOV). This concise set of instructions can be combined to implement loops, arithmetic routines, and complex control structures. Moving to a 6-bit instruction from the original 8-bit allows the use of single IC hex inverters and decoders, reducing chip count. It also reduces the ROM array board space all while keeping the same number of instructions and increasing register count.

Instruction set

Each register is given a 2-bit address to designate it as a source (SS) or destination (DD) for a given operation. The addressing is as follows:

Data path

A distinctive aspect of the architecture is the use of multiplexers in place of a centralized data bus. Each register’s output is piped into a multiplexer used to select the source for write‑back, while a second multiplexer switches the common register input data between the adder, mux output or immediate data. Because every instruction completes in a single clock cycle, control logic is greatly simplified: the opcodes are decodes with a 1-in-4 decoder, and another decoder is used to select the destination register.

Control logic

Another uncommon design choice is the carry and jump logic. Usually the carry is a flag which is latched on an ALU operation. The flags is then typically cleared on a jump operation. But to keep the IC count down and the control logic simple, the carry is not latched and the jump logic is fully combinational. This has to be accounted for when programming: if the destination register of the add operation is different than the operands, then the carry remains valid after the add instruction, but will not be cleared unless the operands are updated.

Moreover, due to the lack of a non-conditional jump, it is possible to ensure the carry is clear and guarantee a jump is performed by either setting the x or y register to 0. It should be noted that the carry input is only passed to the adder on an add instruction, and will not be taken into account for a conditional jump. Hence if the carry input is enabled and an overflow by 1 occurs, a conditional jump with the same operands will consider the carry as being clear. A more detailed look of the control logic is shown...