Several NGFF FPGA core modules and verification boards

Use T113-S4/RK3506G2+XC6SLX25+512M DDR3 to divide the video data of framebuffer into 6 outputs from lvds. 6 displays use GW1NSR-LV4CQN48.

ElecLab • 08/26/2025 at 03:54•0 Comments

- 45nm XC6SLX16/25/45-CSG324 + 512MB DDR3

- 28nm XC7S50-CSG324 + 512MB DDR3L

- 55nm GW2AR-LV18 QFN88 package integrating 20K LUTs/166MHz 64Mbis x32 SDRAM

- 22nm GW5AR-LV25 BGA256 package integrating 23K LUTs/1066Mbps 128Mbis x16 HyperRAM

- 28nm SA5Z-30-D1 BGA213 package integrating 32K LUTs/800Mbps 128Mbits x16 DDR2/200MHz Cortex-M3.

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08/26/2025 at 03:10 • 0 comments

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