T113/RK3506+XC6SLX drives multiple LCD screens

- 45nm XC6SLX16/25/45-CSG324 + 512MB DDR3  

- 28nm XC7S50-CSG324 + 512MB DDR3L  

- 55nm GW2AR-LV18 QFN88 package integrating 20K LUTs/166MHz 64Mbis x32 SDRAM  

- 22nm GW5AR-LV25 BGA256 package integrating 23K LUTs/1066Mbps 128Mbis x16 HyperRAM  

- 28nm SA5Z-30-D1 BGA213 package integrating 32K LUTs/800Mbps 128Mbits x16 DDR2/200MHz Cortex-M3.

The FPGA part leads to 28 pairs of LVDS lines, all of which are equilength wiring on the front and back.

RK3506G2 leads to 2x100Mbps PHY/2xUSB/SDIO/2Lanes MIPI DSI/19xRMIO/2xADC, and its 16bits DSMC/RGB24 interface is connected to FPGA. You can choose to use FPGA as a bus device or RGB 24bits video cutting.

The 7-inch MIPI DSI display verification board leads to 2x100Mbps RJ45/2xUSB/WIFI6/USB 4G/GPS module NGFF socket/MX3.0 socket (CAN/RS485/16xIO PCA9535)/6 P capacitive touch screen/speaker

We will upload the Kicad schematic, but the Kicad file of the PCB will not be open source for commercial reasons.

This motherboard can verify the LVDS split output of T113-S4/RK3506G2 + XC6SLX25, and 6 NGFF sockets can connect 6 1.9" GW1NSR-LV4 displays.

RTC/horn/WIFI6/USB are available, and the TypeC port can be connected to the computer to power the motherboard and UART debug.
We can use it to achieve functions similar to rgb tube clock. Of course, video decoding playback/GIF playback can also be used after inserting the core board of T113-S4.
Similarly, the Kicad file will be uploaded to github later.

The download software of GW1NSR-LVC4QN48 can choose the download port of FT4232, so we designed a 2xJTAG+2xUART download line using the FT4232 chip. Of course, it can also be used for xilinx download, but it needs to burn another .bin file to EEPROM, and xilinx can only use port A of FT4232.
The terminals of JTAG use 6P 1.0mm/1.25mm/2.54mm three spacing connectors, and the VREF voltage can be adaptive from 1.2V to 5V.
UART voltage is adaptive from 1.5V to 5V. C port UART can choose JTAG's A port VREF or 3.3V, and D port UART can choose JTAG's B port VREF or 3.3V. The 3P terminal also has three specifications: 1.0mm/1.25mm/2.54mm.
Kicad files and EEPROM.bin files will be uploaded to https://github.com/eleclab-rpi/FPGA_FT4232HQ_2JTAG_2UART later

The hardware design welding work has been basically completed after many modifications, and we will introduce it from the smallest display unit.

At first, we needed to install multiple 1.9-inch displays on the machine to display simple counting information. I thought of T113-S3/RK3506G2 + XC6SLX for Linux framebuffer video cutting, and then sending it from lvds to multiple small displays, which only needs to maintain the Linux application.
We chose a cheap QFN48 small chip-->GW1NSR-LV4CQN48, which is QFN48 packaged and easy to design and weld. It has 4K LUTs that can fully meet micro applications, and it also has built-in 100MHz Cortex-M0 and 64Mbits HyperRAM. Input data from lvds and output from MCU I8080/MIPI LCD interface. LCD interface We have equipped with 30P MCU I8080 interface and 1.9" 170x320 8bits I8080 LCD screen. We also selected a 1.6" 400x400 12Pins 1Lane MIPI round LCD screen as a reserve. I have set up aWS2812B ambient light for it. A 24Pin OV5640 2Lanes MIPI camera interface is also reserved for future verification.
Another new version has been modified, and we have added a terminal 100R resistor to the input of the MIPI CSI camera according to the original FAE prompt.
We will prepare Kicad's design files later and they will be placed under https://github.com/eleclab-rpi/FPGA_GW1NSR_LV4_1.9-_LCD.