SimTTL is a very simple simulator for TTL circuits to display the timing behavior similar to a logic analyzer. The GUI looks familiar to anyone programming and simulating Xilinx FPGAs. SimTTL that can load KiCad-9 netlists to create an internal model. File names embedded in the schematics can be used to automatically load binaries into RAMs, ROMs or GALs for the simulation. A text file can provide the mnemonic information for a very simple disassembler.

Background

After a friend demonstrated his "Ben Eater 8bit Computer" to me, I got hooked into TTL computer designs. There are a number of examples, where people built a processor out of TTL chips. Another nice one is the "Gigatron – TTL microcomputer". While the first one just uses adder chips for the ALU, the Gigatron uses a combination of multiplexers and adders to achieve more functionality. I wanted to nice time diagrams of their functionality, and the idea was born to write a little program to do that.

So, the first attempt was creating a nice GUI that is close to what I used to work with for FPGA designs and then hardcoded the 2 schematics as examples. So far, so good. The next step was using the new tool to analyze and debug my own schematics, which required a KiCad-9 netlist import. Here is now a version, that helped me a lot and can be helpful for others as well.

Description

1. GUI

The layout is very simple. The main area is occupied with the signal time graphs. Left of that are the names and the values at the main cursor location. Single line signals are represented by an oscilloscope-like graph with the area below logic high filled to differentiate the high state from a low state.

Enumerated signal groups are handled as a bus system and displayed together as high and low lines with transitions and the numerical value in between. The simulation handles not only H and L levels, but also Z (high impedance) and U (undefined). The last one can occur when multiple outputs are active with different levels or inputs are open. Z and U are made visible in different colors (blue and red).

There is a typical main menu at the top and a row of easily recognizable tool buttons.

Bus groups can be expanded or collapsed again all at once with a pair of the tool buttons on top or individually at the + or - sign to the left of the name. In the screenshot above the expansion shows which individual signal of the bus was undefined. This can help to find the root cause.

Signals can be selected by left-mouse-clicking on the name. CTRL and SHIFT can be used to select multiple signals.

Selected signals can then be moved to a new position while holding the left mouse button down, moving to the new position and let the left mouse button go. If the selected signals are at the bottom and have to be moved to the top of a long list, use the mouse wheel to scroll while keeping the left mouse button down.

Right-clicking on a signal brings up a context menu which allows changing the radix of the displayed value. "Invert" inverts the bits before conversion and "Reverse" reverses the bit-order. This allows some flexibility for the value display.

"Highlight" highlights a signal permanently until unchecked. In contrast to a selected signal, which loses the highlighted display when clicking somewhere else, this Highlight can be used as a permanent marker.

2. File Menu

The file menu offers 2 major sources for loading a schematic: Hardcoded built-in or KiCad 9 Netlist. Clicking on the netlist import will show and OpenFileDialog to navigate to the netlist file. Previously opened files will be listed to the right of the import menu item for quicker access.

Once a schematic had been loaded and simulated, it can be stored with all wave forms as a SimTTLFile. Few sample files are provided in the bin-folder, which can be loaded from the file menu.

Saving the current settings will write all current GUI settings to the XML file for this schematic to be automatically loaded at...