Project Logs

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• Survived the DFM gauntlet

  Hiroyuki OYAMA • 11/01/2025 at 16:49 • 0 comments

  I ran exhaustive checks using JLCPCB’s online DFM tool and revised the design until it was fully manufacturable for both PCB and SMT assembly.

  Some traces were redrawn to flow more naturally, some issues were patched or adjusted with minor compromises, and a few alignments had to be intentionally broken to make things fit.

  All major risk points (Dangers) have been cleared, and the remaining Warnings are within acceptable limits for production.

  After going through this process, the overall routing feels cleaner, and the entire circuit design now looks more coherent and balanced.

• All Components Placed, Routed, and DRC Cleared

  Hiroyuki OYAMA • 10/29/2025 at 15:52 • 0 comments

  The UI board is now fully routed — every component has been placed, all nets connected, and the design passes DRC with no errors.

  This was by far the most complex part of the Darśana hardware: 64 potentiometers, 32 key switches, 96 LEDs, four ADCs, two IO expanders, OLED, and all the SPI buses packed into a 4-layer board.

  Careful power segmentation paid off:
  

  • +3V3_UI and +3V3_UI_A rails separated and thickened to 1 mm
  • +5V_SYS → +5V_UI_LED isolated via 100 mΩ resistor
  • VREF and ADC lines shielded with GND guards
  • IOX inputs protected by RC (150 Ω + 1 nF) and 10 k pull-ups

  After endless nights of routing and revising, the DRC finally came back clean.

  Next step: a slow, quiet design review — then it’s time to generate Gerbers and send the first UI board to fabrication.

• UI Board LED Routing Complete

  Hiroyuki OYAMA • 10/27/2025 at 14:10 • 0 comments

  Today I completed routing all 96 LEDs on the Darśana UI board, including those for the key switches.

  The southern “dead-end” section turned out to be the biggest challenge, but all LED chains are now fully connected. With this, all display-related circuits — LEDs and OLED — are now wired and ready for verification.

  To prevent interference with the analog input section (ADC / VREF), the LED layout follows a layered structure:
  

  • LED signal lines are routed on the bottom layer,
  • Analog VREF and potentiometer wiper lines remain on the top layer,
  • and a continuous L2 GND plane is placed between them to minimize coupling.

  This approach allowed me to arrange 64 potentiometers, 32 key switches, and 96 LEDs in a high-density layout while keeping the overall circuit structure well organized.

  The next steps will be:
  

  • placing LED drivers at the origins of each LED chain,
  • completing the SPI routing (SCK / TX / RX / CS), and
  • refining the inner2 power plane for +3V3_UI_D, +3V3_UI_A, and +5V_UI_LED.

  Now, every visual element on the UI board finally has a clear path for light to travel.

• Input System Wiring Complete

  Hiroyuki OYAMA • 10/26/2025 at 14:58 • 0 comments

  The UI board has finally passed its steepest mountain —
  

  all potentiometer, ADC, key switch, and I/O expander connections are now fully routed.

  This section was particularly challenging:

  • 64 analog potentiometers (each with low-pass and reference routing)
  • 32 independent key inputs through two MCP23S17 expanders
  • Integrated ESD paths, shielding traces, and shared ground planes
  • 96 LEDs to coexist in the same grid

  After many iterations, I managed to fit everything while preserving:

  • Continuous ground on inner layer (L2)
  • Reserved space for LED horizontal buses (Bottom layer)

  Next, I’ll start routing LED data and power (L3) —
  but with the entire input system already verified, I feel the design has crossed its biggest hurdle.

• Where Analog and Digital Share the Same Dance Floor

  Hiroyuki OYAMA • 10/21/2025 at 14:51 • 0 comments

  Exploring the physical limits of Darśana's  UI board.
  
  Placing every component directly on the PCB to search for the balance between ergonomics, circuit constrains, and visual rhythm.
  64 potentiometers, 32 key switches, and 96 LEDs - all living toghether on a single mixed-signal board.

  The challenge is not only routing signals, but also shaping the flow of analog and digital currents without splitting grounds.

  This is where engineering and composition meet: how to make every path quiet, logical, and beautiful at the same time.

• Main Board Layout Nearing Completion

  Hiroyuki OYAMA • 10/18/2025 at 18:20 • 0 comments

  The main board of Darśana is almost complete.

  This revision focuses on refining the audio power and signal layout, separating AGND/DGND domains, and finalizing the analog output paths (DAC → Line / Phones).

  • Introduced a local `+5V_AUDIO_Analog` plane on Inner2 exclusively for the headphone amp (TPA6130A2).
  • This simplified routing and reduced coupling around the charge pump region.
  • Maintained at least 2mm clearance between the charge pump loop (CAPP/CAPM/VNEG) and all power traces.
  • Ensured continuous AGND on Inner1, no necks or splits.

  With all components placed and DRC passing cleanly, the PCB measures 294 × 99 mm — fitting perfectly inside the planned 296.6 mm internal width enclosure.

  It was a demanding phase, but the layout came together faster than I expected — a relief, honestly. There are still rough edges to refine, and I can already see places that could be improved with more polish. Fortunately, there’s no rush. I’ll take as much time as needed to make it right.
  

• Layout work has begun

  Hiroyuki OYAMA • 10/15/2025 at 16:07 • 0 comments

  I’ve only ever designed small, simple PCBs before, so this is a completely different scale—and I’m often unsure what I’m doing. Still, with the help of my LLM assistant and all the advice buried in forum archives, I’m somehow managing to keep going.

  • Decided the placement of the main connectors, the Pico, and the 30-pin FFC board-to-board connector
  • Fought through the maze around the USB Type-C connector footprint
  • Routed USB D+/D- to the Pico 2
  • Placed the DAC / AMP power supplies
  • Connected the I2S lines for the DAC

  To make these routes flow more naturally, I completely reorganized the Pico pin map, arranging it so that the UI bus(SPI0, SPI1) comes out on the right side and the DAC/AMP bus(I2S, I2C) on the left—much cleaner now.

  Still feels like it’s never going to end.
  
  
  

• Datasheet review and I/O adjustments

  Hiroyuki OYAMA • 10/12/2025 at 14:17 • 0 comments

  Spent the day checking every circuit against datasheets to match the reference designs.

  Found and fixed several minor issues—and even a few critical ones.

  Review always pays off.

  Also:

  • Line / Phones Out changed to 6.35 mm jacks.
  • MIDI IN / OUT upgraded to full-size DIN-5. I like small parts, but here I prefer the big ones.
  • SPI chip-select pins were rearranged for a cleaner layout and domain separation.
  • Added provisions for EMI filtering on all external connectors — not needed yet, but ready when it is.

• Power & USB Update

  Hiroyuki OYAMA • 10/11/2025 at 15:20 • 0 comments

  • Designed the power circuit for the split-board configuration, separating the Main board (Audio + I/O) and the UI board, which carries multiple ADCs, 64 potentiometers, 32 key switches, and many LEDs — the most complex and costly part of the system.

    By isolating the UI board, debugging becomes easier and re-spin cost is significantly reduced.

  • During pin assignment cleanup, one GPIO line became available and is now assigned to UART1 TX for MIDI OUT.
  • Added ESD protection for the USB Type-C data lines (PRTR5V0U2X-ES + ACM2012-900-2P-T002).
  • Currently in datasheet and wiring verification phase before moving to PCB layout.

• Every Pin Counts — Schematic Complete and Panel Layout Fixed

  Hiroyuki OYAMA • 10/10/2025 at 12:48 • 0 comments

  The full schematic for Darśana is now complete — and the Pico 2’s GPIO pins are completely exhausted.
  

  Every single pin now has a dedicated role: ADC channels for 64 knobs, SPI buses for LEDs and OLED, chip selects for four ADCs and two I/O expanders, I²S for the DAC, and even the line and phones detection inputs.

  There are simply no free pins left.
  

  At the same time, the number of parameters I wanted to control kept growing.

  Designing Darśana became a constant balance between expressive control and hardware limits — a reminder that constraint can drive creativity.

  In parallel, the front-panel design reached its first complete layout.

  The knob arrangement is now mostly fixed, giving a clear sense of how the instrument will feel in the hands.

  Seeing the schematic and panel evolve together made the project finally start to feel real.

  Next, I’ll carefully review the schematic again against all component datasheets, and then request an external design review before moving to PCB layout.

  It’s the moment where ideas must prove themselves in actual copper and traces.
  

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