Digital Logic Design Rule 1:
Don't load outputs with large capacitances - it slows the edges and can cause metastabilities.

Digital Logic Design Rule 2:

Don't connect a logic gates output to its input.

Digital Logic Design Rule 3:

Don't connect gates in a loop unless you have inputs to control the latching.

Digital Logic Design Rule 4:

Never connect outputs to each other.

This sinusoidal oscillator realizable with a CD4069UBE breaks rule 1 twice, rule 2 twice, rule 3 once, and rule 4 5 times.

So how does this work?
Inverters 3 and 4 produce a VCVS which operates as an IVF - an Inverting Voltage Follower. 1 and 2 are VCCS also known as inverting single-input transconductance amplifiers.  Their current output is integrated by the capacitor. This configuration will be familiar to anyone using LM13600 or LM13700 to build VCO's and VCF's.  So the ring 1, 2, 3 form a 2 integrator loop with a 180 phase shift. With the right control this ring can be made to oscillate stably. 6 can be thought of as a resistor to the half-rail voltage. The challenge with the integrator loop is to keep it oscillating.

A source of positive feedback is required to offset any losses due to the non-matched transconductance of the gates. This is provided by inverter 5. Sometimes this is described as modeling a negative resistor. Inverter 6 is the resistance (energy loss) it is trying to cancel. The series resistance makes sure there is more positive feedback than loss which causes the oscillation to grow. The soft non-linearities of the CMOS inverter mosfets at higher amplitudes prevents the outputs from hitting the rails.  The amplitude, signal growth rate and distortion can be adjusted by changing the resistor.

The frequency of oscillation can be controlled by changing the power supply voltage to the all the gates. This will change the output amplitude too and also potentially change the conditions of oscillation.
Alternatively inverter 2 can be replaced by an inverter in a different package so it is the only inverter with its transconductance modules.

Another way to become more familiar with this circuit is to recognize that inverters 1, 3, 4, 5 and the right hand capacitor form a gyrator-simulated inductor.  Inverters 2, 3 and the left hand capacitor simulate a capacitor and resistor in what can be modeled as an RLC oscillator.

With careful layout (e.g. dead bugging), you can omit the capacitances altogether and the system will oscillate at about 5MHz using the intrinsic input, output and pin capacitances.