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Zilog Z80 SBC using VHDL

Z80 production stopped few years back. Still we can create the Z80 CPU based SBC with internal ROM, RAM and UART all inside the FPGA by VHDL

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Using a single programmable device we can create the Z80 CPU, ROM, RAM and UART all inside the programmable chip. We can select the CPU speed using PLL. It is much easier and scallable and does not requires any physical inventory of CPU, RAM, RAM and UART devices.

Zilog Z80

Another legend from the 8-bit era, this processor powered the first portable computer as well as the beloved “Trash-80”  Two years short of the Z80's 50th birthday, Zilog has called it curtains on the 8-bit MPU. 

There are alternative solutionsare there. But to build a complete SBC or system based on Z80 requires additonal memory, decoder, UART, etc.,

SIMPLE Z80 SBC with 8kB ROM, 8kB RAM and UART

It is much easier to design and implement a Z80 SBC with ROM, RAM and UART all inside a FPGA using VHDL.

This project is based on the Aaron Brady's Z80 in the year 2016

The VHDL core used is T80 CPU which was created on Apr 21, 2002 by Daniel Wallner

SPECIFICATION:

  • PROCESSOR:              Z80
  • PROGRAM MEMORY: 8kB
  • SYSTEM RAM:             8kB
  • COMMUNICATION:    UART
  • I/O PORT:                     144, 145

The wrapper around Z80 can be seen at  Gist

Z80 will have Microsoft BASIC V4.7b which fits into the 8kB ROM address space and the BASIC will use some memory in RAM for STACK, STATUS. The user program also goes into the RAM address space.

The VHDL project was compiled using both Quartus version 9.1sp2 and 18.1 and working properly. We can implement more RAM and ROM along with additional features using higher Logic Elements and internal RAM available from the same family.

TARGET BOARD:

EP4CE6E22 with EPCS4 and CH340C
  • FPGA: EP4CE6E22C8N
    • Logic Elements (LEs): 6,272
    • PLLs: 2
    • Embedded Memory: 276,480 bits
    • I/Os: 91
    • Package: 144-LQFP
  • USB-to-Serial Interface: CH340C
    • FPGA TX pin: PIN_10
    • FPGA RX pin: PIN_23
  • Clock Sources
    • 50 MHz: PIN_24, PIN_25
    • 27 MHz: PIN_90, PIN_91
  • Push Buttons (Active-Low with Pull-Ups)
    • FPGA Reset: PIN_88
    • 4x User Buttons [3:0]: PIN_73, PIN_80, PIN_89, PIN_114
  • LEDs (Active-Low)
    • 5x LEDs [4:0]: PIN_1, PIN_2, PIN_3, PIN_7, PIN_11
  • On-Board Storage
    • Altera EPCS4N (Serial Configuration Device)
    • Winbond 25Q64JVSIQ (64 Mbit / 8 MB Serial NOR Flash)
  • Power Supply
    • +5V via USB Type-C connector
    • 4x AMS1117 LDO voltage regulators: +3.3 V, +2.5 V, +1.8 V, and +1.2 V outputs
  • Bitstream Programming
    • via a JTAG socket for USB Blaster

RTL:

After compiling the VHDL code we can see the RTL view

RTL

In the RTL view we can clearly see the main blocks used in the design such as T80 CPU, ROM, RAM, UART and IO.

If we init the ROM with BASIC V4.7b HEX file, then the HEX file will be automatically loaded into ROM and start running during configuration.

Onboard there are 2 clock sources available. 50 MHz(pin24/pin25) and 27 MHz(pin90/pin91). Each source connected to two clock input pins. We can use either one of them. In this case the clock connected to pin#24 which corresponds to 50 MHz input.

set_location_assignment PIN_24 -to clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk

 The board used already having CH340C onboard. We just need to assign the Tx and Rx pins.

set_location_assignment PIN_23 -to rxd1
set_location_assignment PIN_10 -to txd1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rxd1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to txd1

The system RESET is assigned to  

set_location_assignment PIN_88 -to n_reset
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to n_reset

 There are only 5 LEDs available onboard. Either we can use the onboard 5 LEDs or assign different pins for LEDs

set_location_assignment PIN_34 -to leds[0]
set_location_assignment PIN_32 -to leds[1]
set_location_assignment PIN_30 -to leds[2]
set_location_assignment PIN_76 -to leds[3]
set_location_assignment PIN_77 -to leds[4]
set_location_assignment PIN_85 -to leds[5]
set_location_assignment PIN_98 -to leds[6]
set_location_assignment PIN_100 -to leds[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds[6]
set_instance_assignment...
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MC6850_Datasheet.pdf

6850 datasheet

Adobe Portable Document Format - 397.86 kB - 02/08/2026 at 08:50

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Z84C0006PEG.pdf

Zilog Z80 CPU datasheet

Adobe Portable Document Format - 1.33 MB - 02/08/2026 at 08:45

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03_5button_27MHz.jpg

JPEG Image - 387.40 kB - 01/20/2026 at 07:34

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02_50and27MHz.jpg

JPEG Image - 404.13 kB - 01/20/2026 at 07:34

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06_clk_vb_flash.jpg

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  • 1
    FIRMWARE update

    The CH552G based FPGA/CPLD configuration device are very popular due to very low in cost and stable operation. If we have CH552G device and operating under windows 10/11, it is better to upgrade the firmware.

  • 2
    Quartus II download and install

    Since Quartus II 9.0, Cyclone IV E devices are supported. So we can download anything above 9. 

    There is no advantage of downloading the latest Quartus II except it occupies more space and runs slowly compared to the Quartus 9.

  • 3
    Download project files

    Download both Quartus II  9.1sp2 and Quartus II 18.1 version files from the projects software link above.

    We can use Quartus II 9.1sp2 file in Quartus II 18.1 without any issues. During the start up, the Quartus will ask the user to upgrade the IP blocks. But it is not critical or not required and we can ignore.

View all 5 instructions

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