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KiCad Automated Routing Tools

Python and Rust tools to help you or AI route your KiCad PCB

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Wouldn't it be great to have a "Route airwires" button in KiCad that just instantly routed all the tracks on your PCB for you? We're not yet at the point where such a tool is possible, except for the simplest of boards. PCB routing is complicated! (Ground and power planes, via placement, decoupling with low inductance, differential pairs, length matching, BGA fanout, wider power tracks, impedance matching, return currents, spacing for noise prevention, etc. - not to mention cleverly getting everything to connect in a limited space without violating DRC!) Plus, you want some control over how your board is routed - your experience is valuable and only you understand what the final product needs to be. But at the moment KiCad does almost nothing to help you route your board. This project is about developing the tools that will let you (or you+AI) route a KiCad PCB more quickly, while keeping the quality high.

A full suite of Python-based tools, plus a fast Rust backend, for KiCad PCB routing.

Example:

python route.py kicad_files/input.kicad_pcb kicad_files/output.kicad_pcb --nets "Net*" --power-nets "*GND*" "*VCC*" "+3.3V" --power-nets-widths 0.4 0.5 0.3 --track-width 0.2 --via-size 0.4

Features:

  • Grid-based A-star pathfinding with Rust acceleration (~10x faster than Python)
  • Octilinear routing - Horizontal, vertical, and 45-degree diagonal moves
  • Multi-layer routing with automatic via insertion
  • Differential pair routing with pose-based A* and Dubins path heuristic for orientation-aware centerline routing
  • Rip-up and reroute - When routing fails, automatically rips up blocking routes and retries with progressive N+1 strategy (tries 1 blocker, then 2, up to configurable max). Re-analyzes blocking tracks after each failure for better recovery. Also triggers rip-up when quick probes detect blocking early, before attempting full routes.
  • Blocking analysis - Shows which previously-routed nets are blocking when routes fail
  • Stub layer switching - Optimization that moves stubs to different layers to avoid vias when source/target are on different layers. Works for both differential pairs and single-ended nets. Finds compatible swap pairs (two nets that can exchange layers to help each other) or moves stubs solo when safe. Tries multiple swap options (source/source, target/target, source/target, target/source) to find valid combinations. Validates that stub endpoints won't be too close to other stubs on the destination layer.
  • Batch routing with incremental obstacle caching (~7x speedup)
  • Net ordering strategies - MPS (crossing conflicts with diff pairs treated as units, shorter routes first using BGA-aware distance; uses segment intersection with MST for non-BGA boards), inside-out (BGA), or original order
  • MPS layer swap - When MPS detects crossing conflicts (nets in Round 2+), attempts layer swaps to eliminate same-layer crossings. Tries swapping both the conflicting Round 2 unit and Round 1 unit. Re-runs MPS after swaps to verify conflict resolution
  • BGA exclusion zones - Auto-detected from footprints, prevents vias under BGAs
  • Stub proximity avoidance - Penalizes routes near unrouted stubs
  • Track proximity avoidance - Penalizes routes near previously routed tracks on the same layer, encouraging spread-out routing
  • Vertical track alignment - Attracts tracks on different layers to stack vertically (on top of each other), consolidating routing corridors and leaving more room for through-hole vias
  • Adaptive BGA setback angles - Evaluates 9 setback angles (0°, ±max/4, ±max/2, ±3max/4, ±max) and selects the one that maximizes separation from neighboring stub endpoints, improving routing success when stubs are tightly spaced. Uses 0° when clearance to the nearest stub is sufficient (≥2× spacing), only angling away when stubs are too close
  • U-turn prevention - Prevents differential pair routes from making U-turns (>180° cumulative turn)
  • GND via placement - Automatically places GND vias adjacent to differential pair signal vias for return current paths. The Rust router checks clearance and determines optimal placement (ahead or behind signal vias)
  • Target swap optimization - For swappable nets (e.g., memory lanes), uses Hungarian algorithm to find optimal source-to-target assignments that minimize crossings. Works for both differential pairs and single-ended nets
  • Schematic synchronization - When specified, updates KiCad schematic files with any pad swaps (target swaps or polarity swaps) to keep schematics in sync with PCB. Handles multi-unit symbols correctly by updating all schematic files containing the lib_symbol. Disabled by default
  • Chip boundary crossing detection - Uses chip boundary "unrolling" to accurately detect route crossings for MPS ordering and target swap optimization
  • Turn cost penalty - Penalizes direction changes during...
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  • Comparison to FreeRouting

    haas02/04/2026 at 02:13 1 comment

    FreeRouting is another KiCad plugin that can do auto-routing. It's not bad, just more limited in scope, slower, and less integrated into KiCad. It has been around for a while though so is solid and reliable. 

    For simple boards, there's not much difference in what it would do vs. this project, except KiCadRoutingTools gives you more control over track widths, power nets, ground/power planes, etc. 

    This is a relatively simple board routed with KiCadRoutingTools:

    And here is FreeRouting on the same board:


    But for a more complicated board the differences are more apparent. Here again is the board I posted about recently, with bus routing enabled in KiCadRoutingTools:

    And here is FreeRouting on the same board:

    FreeRouting actually failed to route 4 of the nets here. And it took it ~10 minutes. KiCadRoutingTools took ~1 minute and routed all tracks.

    KiCadRoutingTools gives tracks that are far more natural and organized than the Manhattan-style FreeRouting algorithm.

  • Smarter and prettier routes

    haas02/02/2026 at 23:32 0 comments

    Auto-routers are known for producing ugly tracks. I'm working hard to teach this one how to be smarter and prettier. And it's not just esthetics. It can now route dense boards most auto-routers would choke on!

    I've recently added some features that we humans rely on:
    - Preferred direction by layer
    - River routing, with nearby tracks being encouraged to follow a neighboring track on the same layer
    - Rip-up memory: if you needed to rip up a track to route in a new track, try not to block where the old track was, since it is likely going to have to pass through there again when it's re-routed

  • A KiCad Plugin GUI

    haas01/26/2026 at 20:33 0 comments

    I was impressed how easy it was to make a GUI wrapper for the python/rust backend - here it is. 

    There's a tab for basic single-ended routing, an advanced tab with fancier features, another for differential pair routing, one for bga/qfn fanout, one for GND/power plane, and a place to see the logs from each command. 

    Nets can be selected based on component or name, and be filtered in various ways.

    There's a progress bar, close/cancel button, etc.

    All the results are immediately put onto the live kicad pcb board, and can be undo/redo'ed before saving.

    Plus there's a cool icon that gets put on your KiCad toolbar...

  • Using AI to figure out power nets

    haas01/21/2026 at 19:54 0 comments

    Some nets on a PCB will need to be wider because they need to carry more power. We can easily feed in these per-net widths (in mm) like this:

    python route.py input.kicad_pcb output.kicad_pcb --nets "Net*" \
      --power-nets "*GND*" "*VCC*" "+3.3V" \
      --power-nets-widths 1.0 0.5 0.35

    But going through a whole board and figuring out which nets need to carry what amount of current/power and then listing them is tedious, and error-prone. Automating the discovery and categorization is challenging though, because there are so many types of components and situations that arise. For instance, a regulator may output through a fuse, an inductor or ferrite bead, a current shunt resistor, and then eventually get to an IC. Along the way there are various decoupling caps, resistors branching off going to an LED, etc. A script would have a hard time figuring out what nets in this web need to carry large currents. First of all, it would need to understand what each component is and does, more or less. What are the typical currents needed by that kind of IC? How much is used in that LED? 

    An experienced human, even if they're not the original designer, can go through and figure it out pretty well. They know what each component is, and if not they can look it up based on the part number and check the datasheet. And they understand how current flows through a branching circuit like this and what nets will need the larger widths. But again, it's tedious, and transcribing that into a list of net names and widths is error-prone.

    Fortunately, it turns out AI is already very capable of analyzing such a board and doing this job of understanding power flow pretty well! Here's an example of how it works and what it looks like in practice. More details here.

    First, start up a claude code session. Next, we point the provided claude skill at the kicad pcb file: /analyze-power-nets input.kicad_pcb, and it goes to work. First it extracts info from the kicad pcb file about what components are on the board and how they're connected (not routed, but what airwire nets "conenct" what), using a python script. It categorizes all the easy components like resistors, caps, inductors, etc. and then searches the Web for info about each non-trivial component. This all takes about ~15 seconds, since components are researched in parallel. 

    Next, it forms an understanding of what the board is trying to do! Here's it's correctly identified that this is a PIC programmer. It then traces the power flow through the components on the board, and estimates the power/current and voltages in important nets, based on info it learned reading the datasheets

    It then reports what it has discovered and surmised, and determines the width of each trace needed based on power requirements and IPC-2152 guidelines. It finally outputs a command in the correct format to be used by the --power-nets --power-nets-widths commands.

    In the end it took just ~20k tokens to do all that for this (simple) board. The result after routing with the --power-nets --power-nets-widths commands given looks pretty reasonable!

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Discussions

AVR wrote 5 days ago point

Yes this is the kind of stuff we need !

  Are you sure? yes | no

haas wrote 02/04/2026 at 02:34 point

Thanks for your suggestion! I've added a log here about that now.

  Are you sure? yes | no

Robert Gawron wrote 02/03/2026 at 21:41 point

Nice project! I think it would be great to make a comparation on some PCB an results from this project and Freerouting tool (AFAIK standard for open source/free tools for that). Would be great to see where ne tool is better than other.

  Are you sure? yes | no

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