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RTL lib 1.0 Release

A project log for Play FPGA like Arduino

Bring open source soft-core MCU into FPGA, enjoy flexibility and customization like no other

Changyi Gu 03/31/2017 at 07:480 Comments

RTL lib 1.0 is released on GitHub, with the following peripherals:

*) ADC: ADC for Altera MAX10

*) BCD: Binary Codec Decimal

*) block_memory: BRAM inferred

*) chip_ID: chip ID for Altera MAX 10

*) codec: voice codec

*) debug_counter_led: counter and led for debug

*) FASM_register: register for Wishbone FASM

*) flash_loader: module to load image into CFM

*) interrupt: interrupt controller

*) SD: MicroSD card controller

*) SRAM: Serial SRAM

*) SRT_DIV: radix 4 SRT division

*) switch_debouncer: button debouncer

*) timer: 8051 timer

*) UART: Async Serial port for 8051

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