Architecture Overview

APEX-16 is a 16-bit pipelined CPU designed from scratch in Digital, a logic circuit simulator. The core design focuses on instruction-level parallelism through a 6-stage pipeline that can process multiple instructions simultaneously.

Pipeline Design

The CPU uses a 6-stage in-order pipeline:

1. Fetch —Retrieve the next instruction from memory using the program counter
2. Decode — Break down the instruction into opcode, operands, and register targets
3. Register Read — Load values from source registers
4. Execute — ALU handles integer operations, FPU handles floating point operations
5. Memory — Load/store operations to RAM; passes through for non-memory instructions
6. Write Back — Write results back to destination registers

Register File

• 16-bit wide registers across the entire CPU
• 1 Accumulator register (A) — primary computation register
• ~8 General Purpose Registers (R1–R8) — flexible storage for operands and results
• RAM addressing registers — dedicated registers for memory access (planned)

Execution Units

Arithmetic Logic Unit (ALU)

• Logic operations: AND, OR, NAND, NOT, XOR
• Shift operations: Left shift, Right shift
• Comparison: Less than, Greater than, Equal
• Integer arithmetic: Addition, subtraction (via adders in Digital)

Floating Point Unit (FPU) — In Progress

• Floating point addition
• Floating point subtraction
• Float format: TBD (standard format planned)

Complex Math Unit (CMU) — Under Consideration

• Potential support for multiplication and division
• Role and implementation still being evaluated

Design Challenges & Solutions

Version 1 Issues (Scrapped)

• Pipeline stall logic became too complex
• Rigid structure with low flexibility
• Tightly coupled components made debugging extremely difficult
• Data hazards (read-after-write) hard to resolve

Version 2 Approach

• Simplified pipeline stages
• Cleaner modularity for easier debugging
• Focus on getting the core pipeline working before adding complexity
• Better separation of concerns between execution units

Known Technical Challenges

• Data Hazards — Managing read-after-write dependencies in the pipeline
• Control Hazards — Branch prediction and instruction flow control
• Stall & Forwarding Logic — Preventing pipeline stalls while maintaining correctness
• Memory Access Timing — Coordinating RAM access through the pipeline

Implementation Details

• Simulator: Digital (by hnemann) — uses built-in adders and logic primitives
• File Format: .dig circuit files

Future Goals

• Complete floating point arithmetic implementation
• Finalize and document the Instruction Set Architecture (ISA)
• Implement virtual memory support
• Write test programs and simulation benchmarks
• Develop a simple bootloader or OS kernel

Inspiration & Learning Sources

• Intel CPU Architecture: i386–Pentium — Core understanding of modern CPU design
• MIT OpenCourseWare Pipelining Lectures — Pipeline architecture theory
• NAND Game — Practical understanding of floating point logic implementation

Current Status

Active development — Version 2. Early stage, focusing on pipeline correctness and core functionality before adding advanced features.