My future goal is to get into MIT and work at AMD/Intel. I was mulling over it and researching on what my 4-year plan(I'm a incoming Freshman) to get into MIT should be. And I realized that designing CPUs by hand in a schematic simulator format is very inefficient. Designing using HDL(SystemVerilog) is way more efficient. I have already finished Digital Design and Computer Architecture by David Harris. This book was exactly what I needed to fully understand the purpose of cache, RAM, and virtual memory. It also boosted my knowledge of pipelining and how to even design one.(There is a full HDL code for a pipelined CPU) So I have scrapped this project and I am and have already started a new 32 bit pipelined CPU with actual virtual memory this time and FPUs and the whole thing. I am gonna post a project on Hackaday VERY soon.