• Log #3: Thermal Stability & Load Testing Analysis

    Mahmoud Al-Bakkar • 08/17/2026 at 19:49 • 0 comments

    Following the gate signal analysis, the next critical validation step for this discrete stepper driver is thermal stability under a sustained holding torque state. Stepper motors draw their maximum current when stationary, placing the highest thermal stress on the H-Bridge MOSFETs.
    Test Methodology:
    The NEMA 17 stepper motor was energized and locked in a holding position. Temperature readings were taken from the heatsinks of the high-side (IRF9540) and low-side (IRLZ44N) MOSFETs over a 10-minute continuous load period. Ambient room temperature was 23°C.
    Thermal Data Results:
    • Initial (T=0): High-side = 23°C | Low-side = 23°C
    • T = 3 minutes: High-side = 30°C | Low-side = 37°C
    • T = 5 minutes: High-side = 36°C | Low-side = 42°C
    • T = 10 minutes: High-side = 40°C | Low-side = 46°C
    Engineering Conclusion:
    The data shows a stable thermal curve that begins to plateau around the 10-minute mark. The heatsinks are effectively dissipating the power .
    Notably, the low-side IRLZ44N runs approximately 6°C hotter than the high-side IRF9540. This confirms our earlier oscilloscope observations: the low-side MOSFET is not only handling the continuous holding current but is also subjected to micro-conduction from the Miller effect and switching losses during state changes. A maximum temperature of 46°C is well within the safe operating area (SOA) of the silicon, proving this discrete architecture is robust enough for continuous operation without active cooling.

  • Log #2: Gate Signal Analysis & Miller Effect Observation

    Mahmoud Al-Bakkar • 08/17/2026 at 19:47 • 0 comments

    In this log, I hooked up a Rigol DS1102E oscilloscope to probe the gate signals of the H-Bridge under no-load switching conditions. The primary goal was to verify the programmed dead-time and observe the switching characteristics of the discrete MOSFETs.
    Observations:
    As seen in the attached trace, the dead-time logic successfully prevents a direct shoot-through. However, a noticeable phenomenon occurs during the high $dv/dt$ transition. The oscilloscope captured a voltage spike of approximately 2V on the low-side IRLZ44N gate when the high-side IRF9540 switches.
    Engineering Analysis:
    This is a classic demonstration of the Miller Effect (induced via parasitic drain-to-gate capacitance C_gd. Because the IRLZ44N is a logic-level MOSFET with a V_gs ranging from 1.0V to 2.0V, this 2V spike is just enough to push the low-side transistor into slight micro-conduction. This perfectly explains the minor 10mA (0.01A) idle current draw visible on the bench power supply during switching, even without a motor connected.
    While this micro-conduction is not fatal and doesn't cause catastrophic thermal runaway at this scale, it is a valuable insight. For future iterations, decreasing the value of the gate pull-down resistors or implementing a dedicated gate driver IC to actively sink the Miller charge will be necessary to achieve a perfectly clean switching state.

  • Log #1: Perfboard Prototyping (V1.0) - Function Over Aesthetics

    Mahmoud Al-Bakkar • 05/02/2026 at 17:20 • 0 comments

    The wiring complexity is intentional and functional. 

    This architecture requires 10 direct control lines from the MCU to drive the individual discrete stages (including the 2N2222 pre-drivers and logic-level low-side gates). 

    Additionally, 3 feedback lines are routed back to the MCU's ADC to read the voltage drop across the 0.1-ohm shunt resistors, allowing for real-time current sensing and active control.