NovaGPU TS1T is an experimental graphics processing architecture written in Verilog RTL, designed for research, simulation, and validation on FPGAs, with potential future evolution to ASICs.

The project explores a combination of classic rasterization, token-based processing, specialized accelerators, and image generation directly from RTL simulation.

Verification Status
Latest results shown:

Total tests: 48
Tests passed: 47
Tests failed: 1
Success rate: 97%
Only one failure pending:

A5 — Handling degenerate triangles within the Triangle Rasterizer
Currently demonstrated capabilities
Rasterization
Functional triangle rasterizer.
Bounding-box traversal.
Pineda-like edge functions.
Write to the framebuffer.
Validated pixel generation.
Geometry
Visual demonstrations:

Rotating 3D cube.

Rotating 3D Tetrahedron.

Generated from RTL simulation.

Visual Generation
The current workflow is:

Repository ↓ RTL Compilation ↓ Simulation ↓ Framebuffer ↓ PPM Export ↓ MP4 Conversion ↓ Final Video

Not used:

Blender
Unity
Unreal Engine
The image comes from the framebuffer generated by the simulation.

Main Components
TMU
Token Matching Unit

Responsible for:

Token Reception
Tag Matching
Data Flow Coordination
Shader Cluster
Executes shading operations.

Tests:

NOP
ADD
MVP Transform
Currently validated.

Triangle Rasterizer
Fragment Generation.

Functions:

Triangle rasterization
Bounding boxes
Pixel coverage
Framebuffer writing
Currently the module closest to 100% implementation.

BVH
Bounding Volume Hierarchy

Validated for:

Traversal
Ray hit
Ray miss
SRAM Controller
Validated for:

Write
Read
Ack
Framebuffer integration
Budget Controller
Computational budget control for complex tasks.

MVU
Motion Vector Unit

Designed for:

Reuse of temporal information
Possible frame interpolation
Motion optimization
New Modules
AFA
Aquatic & Foliage Accelerator

Specialized in:

Vegetation
Procedural motion
Waves
Environmental elements
Testing:

6/6
MPE
Meta Prediction Engine

Experimental prediction system.

Capabilities:

Observation History
Predictions
Prefetch
Tests:

5/5
GIA
Geometry Intelligence Accelerator

Experimental module for:

Geometric prediction
Object tracking
Spatial pattern detection
Tests:

4/4
Nexus
Recently introduced.

Based on what has been shown so far, it appears to be geared towards coordination and interconnection between internal blocks.

PVA
Another new block recently incorporated.

Detailed public documentation is still lacking.

FPGA Synthesis
Previously validated on:

Xilinx Artix-7
Results shown:

Successful synthesis
Successful implementation
Bitstream generated
Next Goal
Based on what you have mentioned several times:

Physical FPGA
Immediate goal:

Tang Nano 9K
Not for running a full GPU.

But to verify:

RTL Correctness
Real Integration
Timing
FPGA → ASIC Flow
Current Demonstration Goal
Generate a complete sequence:

10 seconds
60 FPS final video
Approximately 600 frames
Starting from:

Fast PPM generation
Automatic export
MP4 conversion
With more complex scenes than the initial demonstrations.

Project Philosophy
What distinguishes NovaGPU TS1T from many educational projects is that it attempts to build a complete graphics architecture using open and reproducible RTL:

Source code available.
Reproducible simulation.
Validated synthesis.
Demonstrable visual generation.
Planned path towards FPGA and eventually ASIC.

Currently, the strongest indicator of progress is that the validation went from approximately 33/37 tests (~89%) to 47/48 tests (~97%), with only one known active fault remaining in the rasterizer.