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A project log for Building a GPU from scratch in Verilog

A complete graphics pipeline written in RTL Verilog, built by a single developer using open source tools. Not a soft-core. Not an emulator.

jostinJostin 06/11/2026 at 14:320 Comments

47/48 Tests Passing - Only One Bug Left :p

Today I finally reached 47 out of 48 tests passing on NovaGPU TS1T.

Honestly, I didn't expect to get this far this quickly.

Over the last few days I added several new modules and fixed a lot of integration bugs across the RTL.

New modules currently implemented:

Current validation results:

The only remaining failure is:

Ironically, it could be the easiest bug in the entire project or the hardest one. I honestly have no idea yet XD.

The project is still focused on:

One of the things I like most is that the current visual demos are generated directly from RTL simulation.

No Blender. No Unity. No external graphics engine.

Current demos:

The complete flow currently looks like this:

Clone repository ↓ Compile RTL ↓ Run simulation ↓ Generate framebuffer ↓ Export PPM frames ↓ Convert to MP4

My next goal is improving frame generation speed and producing longer animations directly from the RTL pipeline.

I also plan to scale portions of the design for testing on a Tang Nano 9K FPGA.

Repository:

https://github.com/nova-studios-hw/novagpu-ts1t

Discord:

https://discord.gg/RfQwz8ySr

Thanks for reading

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