This project started in september 2024. It is made only using free, open source software (Kicad, Freecad, Inkscape, Gimp) or free for commercial use (STM32CubeIDE, Vivado).

The current prototype version is the third and works at 100MSps. The next version is to be the last one, it will sample at 200 Msps and include USC-C for power delivery, with improved hardware and case. This version is almost already ready for manufacturing as of june 2026.

Any further hardware modification will only be for bug-correction purposes (if any) without adding new features.

The MCU is based around a Cortex M-7 STM32: the STM32F426. It goes along with a 32-bits SDRAM which is used as frame buffer for the screen. It connects to the screen with a RGB888 parallel bus, to the FPGA using a SPI, to FLASH using QSPI, and to PSU board using I²C.

The sampling system is based around a Spartan7 FPGA: XC7S15. The samples are stored into a 16-bits DDR3 memory. Each canal uses one 8-bits 100MHz AD9283 ADC (two for 200Msps version). The front-end is made of several gain amplifiers, anti-aliasing filter, analog multiplexers, vertical position control, miniature relays and photomos for AC/DC/GND input selections. Bandwidth is expected to be >50MHz. There are one additionnal external trigger input, and one trigger output, also used as a 1KHz probe calibration output (selectable). The input capacitance can be adjusted with trimmer capacitors.

The firmware (STM32) is built around FreeRTOS. The drivers are written "bare-metal" without using HAL drivers. The graphics library is custom, made from scratch and is highly optimised for speed. It takes advantage of DMA2D and ChromeART. It uses triple-buffering. Global performance is about 45-60FPS at almost anytime. The firmware embeds semi-automatic calibration procedure, which allows user to calibrate the vertical input of the scope, for each channel and each caliber. After calibration, vertical precision is < 1%. Basic functions are supported: run/stop modes, superzoom and fast samples shuffle, min/max/avg measurement, FFT, cursors etc. For smaller calibers, a sinc interpolation filter is used, using ARM CMSIS DPS library.

The FPGA is programmed with Verilog/SystemVerilog. Free ARM (Xillinx) IP cores are used for the DDR3, PLL, FIFOs. AXI interface is not used. The sampling sections uses a configurable decimation min/max filter for slower timebases. The interface to MCU use 16-bits lenght SPI, using simple protocol (header + datas). Only the current displayed samples are transfered to the MCU, with the use af a second min/max decimation/compression algorithm.

Work ahead:

- Manufacture last version (200MSps)
- Add RTC
- Add 200MSps support
- Final hardware validation
- Bug fixes