You know you can use logs which offer more formatting options than comments to explain aspects of your project, no?

I didn't know that. Thank you.

I'll continue this in the logs.

First of all, this project would have been entirely different but for Dean Netherton's Dino Boards RC2014 RC80/BP80 Extended Bus Turbo Z80 board. His project solved the problem of interfacing a newer, faster processor (16/20Mhz Z80) to older, slow I/O (3.5/7.0Mhz MSX Bus). His board switches between a higher-speed onboard crystal, and the older, slower bus clock of the RC2014 Bus, on the fly, on the basis of the Z80 bus cycles. Anytime it switches speed, it does a clock stretch to prevent glitching & provides a smooth clock transition. It defaults to higher speed, and when it encounters an I/O operation, it slows the clock down for 32 Z80 T-states. Then it resumes the fast speed. The fast speed is limited by an SP3T switch on the Stegosaur (green) version and by a series of clock-divider-select jumpers on the yellow version. I chose the green version because it was simpler.

As it turns out, the Stegosaur's speed-limiting switch was key to adapting this board for other uses. The pld's he uses to decode bus cycles is ultimately controlled by the signals through that switch: 

1) FASTCLOCK* (/MODE_FAST) - Active LOW to select for full speed (16/20Mhz Crystal Speed w/1 Wait State)

2) SLOWCLOCK* (/MODE_NORMAL) - Active LOW to select slow speed (Bus Clock Speed Native Wait States + 1)

3) Both inactive HIGH to select an intermediate speed. (16/20Mhz Crystal Speed w/3 Wait States)

(Both active LOW appears to be undefined.)

So, besides basic power & ground, and Z80 Signal passthroughs, my interface at a bare minimum had to provide those (2) signals, in the right combinations (LH, HL, or HH).

Other considerations included the RC2014 Bus, which usually includes the (slow) 3.5Mhz bus clock, and 5 Volts/Ground only. As the Z80 board could operate with the interface "freestanding", without the RC2014 Bus, there would be no bus clock to define its slow or "native mode". The  TRS-80 bus clock could therefore be highjacked & routed to the RC2014 Bus connector on the Z80 board, to provide the "native mode" clock. But the Z80 board could still be plugged into the RC2014 backplane, driving not just the bus clock line, but the power & ground lines as well, powered off the TRS-80's power supply. The TRS-80 has +5-volts Vcc & Ground, but it also has +12-volts, which the RC2014 lacks. So I used the SP3T switch that I didn't install in the Z80 Turbo Board, and used it to select an Aux Power line of +5v/Ground/+12v (paired with an Aux Ground) out of the interface, and bring those lines out to a couple unused pins on the RC2014 80-pin interface. 

So now I have (4) signals: Aux Power, Native TRS-80 Clock, Native TRS-80 Clock Select, and Turbo Clock Select; these are all twisted-pair w/Ground wires. Those, plus +5-Volts Vcc Power, Ground, and Z80 passthrough signals, and the interface to Dean's board was defined.

The other side, the interface to the TRS-80, was more of a sticky wicket.

A second consideration concerned the development of the original TRS-80 Model I: early 8-bit processors had no memory management; the entire 64KB primary memory space was open for writing & reading programs & data without restrictions. There was a secondary, limited addressing space for acquiring & outputting data, called the I/O space; this required a separate secondary addressing circuitry (at extra cost) to be used. 

When Zilog released the Z80, they marketed it as part of a "total solution" -- they proposed a variety of chips* that would take care of I/O functions, mostly transparently, without program intervention. Unfortunately, when the TRS-80 was being developed (on a shoestring, without corporate support), those chips were "not ready for prime time" -- still vaporware, really. Other manufacturers had chips that performed similar functions, but they required a lot of expensive connecting circuitry -- "glue logic" -- to work. So the TRS-80 developers decided to make it as cheaply as possible, out of discrete logic.

All useable computers require a resident control program -- the "operating system" -- to provide a defined interface between the hardware & the user programs. The TRS-80 developers chose a BASIC system in ROM with *no licensing fees*, to get it started. The Z80 starts execution at POWER-ON or after RESET at the memory address 0x0000. So that's where they put the ROM. There was no keyboard controller chip available, so they stacked a hard-wired keyboard matrix right into the motherboard, and interpreted it as additional memory locations, under control of the ROM program. There was no video chip available, so they hard-wired an NTSC Black&White (not Color) TV signal that was fed from an incomplete video memory -- they left out one "expensive" 1Kx1-bit Static RAM, & made up for it with a couple of spare gates on the board. Then they provided for up to 16KB of cheaper dynamic RAMs that were refreshed by the Z80's "hidden refresh" signal -- no additional circuitry required. All of this was placed in memory, so no additional I/O decoding circuitry was necessary.

[The video clock circuitry was run off a 10.6445Mhz crystal, which was divided to provide the dot clock, horizontal synching, vertical synching, blanking, & composite video signals for a B&W TV: 16 lines of 64 characters each, each character 5x7 dots in a 6x12 matrix or low-res graphics of 128x192. (3rd-party add-ons had higher resolutions.) Each character/6-block graphic on the screen was given its own memory address. This same video clock was divided down to provide the processor bus clock of 1.774Mhz. Slower than the Z80 could run, but no separate clock circuitry was required.]

They then realized that there needed to be some kind of mass storage. They were already selling cassette recorders, so they added that to the design. There was still no pre-defined interface, so they did finally add one fully-decoded I/O port (hex address 0xff) under ROM control to provide tape storage recorded at 250 baud (upgraded to 500 baud in the Level II, then to 1500 baud in the Models III & 4/4D). But it was not a complete I/O decoding circuit; it was only for that single port (plus a secondary partial port hex address 0xfe used by 3rd-party developers). It only cost a few logic gates, almost at no expense. 

So, of the 64K memory available, the 1st 1/4 was locked in on the ROM operating system, Keyboard, and Video display. The 2nd 1/4 of memory was locked into user program memory, and the other 1/2 wasn't even defined. The basic functions of the system were wired to the memory circuitry -- "memory-mapped" -- and everything was under the direct control of the ROM operating system programs -- "programmed I/O". "The die was cast."

Most other 8080/Z80-compatible systems ran a licensed (paid-for) operating system called CP/M. Typically, those systems would use front-panel switches, punch cards, perforated paper tape, or even floppy disk drives, to load the system into the highest available memory, out of the way of user programs. All user programs could then be standardized to load in the identical lower parts of memory to be run (from hex address 0x0100, up to the bottom of CP/M). Some of these systems included ROMs to load the operating system, but they would turn the ROMs off ("shadow" them) as soon as CP/M was loaded. The original TRS-80 Model I could not do that, so it was not compatible with market standards. But the machine they cheaped out on, the one they expected to sell maybe 2500 of, turned out to be a best-seller. They had to stick with that architecture: 1st quadrant locked, memory-mapped I/O, programmed I/O, proprietary bus.

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*Counter-Timer Circuit w/built-in Interrupt Controller (CTC), Dual-Channel Full-Duplex Serial Communications Controller (SIO), Dual-Port Bi-Directional Parallel Interface (PIO), and Quad-Channel Direct Memory Access Controller, allowing Transparent Data Movement between Memory & I/O without Program Intervention (DMA). All of these were integrated with the Z80 "hardware-interrupt" structure. 

A third consideration was the development of the  TRS-80 Model II: not as a home computer, but developed as a serious business machine, Tandy granted it much more respect, and development money, than it ever did the Model I. The trade-offs and short-cuts in the Model I are nowhere apparent in the Model II. They made full use of the Z80 support chips, plus a keyboard controller, plus a floppy disk controller, plus they added a Motorola Video Controller to the mix. That last one allowed the video to support an industry-standard 80 character x 24 line display. This meant the processor clock no longer needed to run off the video chain, so the processor could run at the full Z80A 4Mhz speed. Memory was left open for both a loadable operating system & user programs; the boot ROM was shadowed as soon as the system was up & running. Maximum-capacity 8-inch floppy disks provided for plenty of "fast" mass storage. Of course, though the system could run CP/M, they still wouldn't pay those licensing fees, so they developed their own proprietary TRS-DOS operating system. 

The one hat-tip to the Model I was the video memory. They still allocated one byte of memory to each screen character, but this time, they tucked video memory away at the top of the memory map, and shadowed it out when not being accessed. So, as designed,  the Model II had a completely useable 32KB or 64KB memory space available to the operating system & user programs. And all the Model II I/O chips took on many responsibilities handled by the lone Z80 in software on the Model I: "I/O-mapped I/O" instead of "Memory-Mapped I/O"; "Hardware-Interrupt Driven" instead of "Programmed I/O". 

If this were all we had to work with, then the easiest thing to do would be to make a separate interface for each machine. But it isn't all.

Coming off the TRS-80 Model II, you'd think Tandy would wise up & throw everything behind that, but not so fast. In the meantime, the Model I had acquired a large array of expansion options & software, and was a major cash cow for Tandy. So when the FCC outlawed further production of the Model I due to RF interference, Tandy was stuck between the proverbial rock & a hard place. Go with the better system, with a limited customer base, or come up with something limited but compatible with a larger customer base. Tandy was a business, so, yeah, they went with the Model III.

The Model III followed essentially the same memory space map as the Model I, 64KB memory, broken into four 16KB memory quadrants: the first locked  to ROM, memory-mapped keyboard, & memory-mapped video; the other three quadrants were dedicated to operating system & user program RAM memory. It provided for 80-90% software compatibility from the Model I to the Model III; further software development approached 100% backward compatibility from the Model III to the Model I. The Model III also continued the Model I approach of programmed I/O, where the Z80 processor had to be involved in all data exchanges with devices.

But the Model III hardware design was significantly different from the Model I. First, it was an "all-in-one" unit like the Model II, including up to two built-in 5.25-inch floppy disk drives in the cabinet. It could also take two external drives. (The Model I could take up to four external 5.-25-inch drives, whereas the Model II could have one internal 8-inch floppy drive, and up to three external ones.) Second, like the Model II, most other I/O was mapped into the I/O space, & selected by a full I/O decoding system -- not memory mapped like the Model I. But it was still mostly discrete logic like the Model I, rather than the I/O support chips in the Model II. The one exception to that is that the Model II video control circuitry was lifted & transplanted to the Model III, although it was programmed to appear like the Model I. This meant the processor clock was no longer tied to the video chain, and the designers were able bring the Z80 processor up to full speed, from 1.774Mhz to 2.02Mhz, with only minor changes to the ROMs. Finally the Model III included a printer port as standard like the Model II (an add-on for the Model I), an isolated I/O bus for peripherals (the Model I was totally unprotected from malfunctioning peripherals with its open bus; the Model II had no peripheral bus to expose it to problems), and connections & support for dual cassette tape recorders for mass storage were removed. Adding a disk controller or RS-232 serial communications port for a modem were kept as options from the Model I configuration process.

So we still have two different memory models: four 16KB memory quadrants with the first one locked, and a limited video screen interface, or open memory in 1-to-2 32KB blocks with shadowing, & an industry-standard video screen. The development of the original Model 4 complicated things.

The Model 4 was intended as an upgrade to the Model III. Same case, painted white instead of grey. Full compatibility with Model III hardware & software. Two operating modes: Model III Mode, & Model 4 Mode. So far, so good.

Extended video memory from 1KB to 2KB: capability of switching to an 80-character x 24 line display, like the Model II. Extended boot capabilities: booting from & using a Model II hard disk; booting from & using an Arcnet network add-on. Powerful Model 4 TRSDOS 6.x operating system.

Now for the sticky point.

The Model 4 (both early non-gate-array version, as well as the later gate-array version, including the Model 4D) has *FOUR* different memory maps. It boots into the primary Model III memory map of four 16KB quadrants, first one locked. During transition to Model 4 Mode, it uses a 2nd memory map where the Model III ROMs can be overlaid with RAM memory. In the third memory map, the whole map is re-mapped (switched) to the Model II map of two 32KB blocks, with the 2KB video memory shoved up to the top; the memory-mapped keyboard is pushed in directly below the video memory; the ROMs are shadowed out. The final full Model 4 Mode has the keyboard & video shadowed out as well. This way, it had all of memory for the operating system & user programs; it could run both the proprietary TRSDOS or the industry standard CP/M and its later developments. In the Model 4 mode, the unit can hold an additional 64KB RAM memory (128KB total), which is shadowed (or "bank-swapped") in & out in 32KB blocks (upper or lower memory). This shadow memory capability was also added into the Model II, as well as its later versions the Model 12, Model 16, & Model 6000. 

Even more confusing is the "transportable" Model 4P (both the early non-gate-array version, as well as the later gate-array version). It has essentially the same maps as the Model 4,  but only a 4KB boot ROM instead of the Model III/4 14KB BASIC ROMs. So it boots into the 1st Model 4 mode, then switches out the boot ROM the way the Model II does, and continues as a Model 4; otherwise it loads an image of the Model III/4 ROMs into low memory, write-protects it, and switches back to Model III mode. So you have similar architectures bouncing back & forth between the Model I/III memory map, utilizing Model I/III signals, and the Model II/4 memory map, utilizing Model II/4 signals. This requires that both modes be built into the interface, that it have the capability of detecting which mode to use, and the cabability of switching modes on the fly.

So. If we are accessing the the original TRS-80 circuitry with the Turbo Z80 board, i.e., the original ROMs & the memory-mapped I/O, we are dealing with old hardware that is relatively SLOW, like the intended I/O on MSX systems. The Turbo Z80 board automatically recognizes I/O-mapped accesses & slows the processor down for those, but it does not recognize the slow memory-mapped accesses. We have to select & decode the relevant TRS-80 conditions and signals, to allow the slowdown to occur for the TRS-80s as well.

Firstly, for all TRS-80 Models, a case-mountable SPST "Master Enable" SWITCH is provided. When open, this switch pulls up an internal control line, allowing operation of the interface as planned. When closed, the switch grounds that control line, disabling the interface, and selecting the slow native TRS-80 clock speed for the Turbo Z80 board.

As we are dealing with accesses to memory-mapped devices, the selection of these devices is ONLY VALID once the memory addresses are DECODED. Unfortunately, many of the dynamic memory REFRESH circuits use the same circuitry as regular memory access circuits. This means we CANNOT just use the memory-select signal MREQ* (expressed as the Memory Row Address Strobe signal -- RAS/RAS*), which feeds several other signals in sequence (the delay NEXT/NEXT*, the multiplexor select MUX/MUX*, and the Memory Column Address Strobe CAS/CAS*), as a "memory-address-valid" signal. Fortunately, those other signals are typically suppressed during a REFRESH cycle, which provides that the later signals CAN be used as the "memory-address-valid" signal. So the second signal used accross the whole interface will be the "valid memory address" signal: NEXT* on the Model Is, Model IIIs, and non-gate array Model 4s, whereas it will be the MUX* signal on the Model IIs, Model 12s, Model 16s, Model 6000s, and gate-array Model 4s. This line will be clipped to an appropriate "leg" of one chip on the TRS-80 being adapted. (location provided in installation instructions)

The last connection for all model TRS-80s is a ground-equalization line, clipped to any available grounding point on the TRS-80 chassis or motherboard.

This cable is attached to the interface (J4) with a 4-pin Dupont connector: Switch+ (pullup), Switch- (Ground), Ground (equalization), and NEXT*/MUX* (valid memory address), with the SPST switch & 2 probe-clips on the other end of the cable. This is for all TRS-80s.

The main unique feature of the Model I & Model III, was the hardwired assignment of the BASIC ROMs (12KB in 1-to-3 chips on the Model I, 14KB in 1-to-3 chips on the Model III);  User ROMs, Interrupt Register, Quad Floppy Disk Select Register, Dual Tape Cassette Deck Select Register, Parallel Printer Port (Status/Data Registers), and Floppy Disk Controller (all memory-mapped on the Model I); and the keyboard matrix & video memory (on both the Model I & the Model III). All of these slow items are in the first quadrant of the memory map. Rather than needing a separate control line for each, it only needs a select line for anything in that quadrant (addresses 0x0000 to 0x3fff) to enable the slowdown to occur, i.e., the top two bits of the 16-bit address bus need (A15 & A14) to be "0". Each of these has a probe clip attached to the TRS-80 address bus.

The other unique feature of the Model I & Model III, was the programmed  I/O. This required the Z80 in the TRS-80 to continually monitor hardware in tight, counted programming "loops", dependent on the speed of the processor, and the counts, and timed out in milliseconds, microseconds, & nanoseconds. The two main conditions for this was reading & recording cassette tapes, and reading & recording floppy diskettes. So the time for detecting those is whenever either one of them has its device motor turned on (CasMotorOn or DskMotorOn) -- no decoding necessary. These lines are pulled inactive low if the cable is not connected. There are two more probe clips to attach to each of these signals.

FInally, if these are the models connected, a stable power connection would be helpful (sometimes older power supplies can get "cranky"). There is a +5-volt Vcc stabilization lead, and a Ground stabilization lead. Each of these is has a probe clip attached to any available Vcc line & Ground line/chassis.

This cable is attached to the interface (J2) with a 6-pin Dupont connector: +5-volts Vcc (power equalization), Ground (equalization), CasMotorOn, DskMotoron, Address A15, and Address A14, with 6 probe-clips on the other end of the cable. This is for all Models I, III, 4, 4P & 4D TRS-80s; this Model I/III Mode cable is removed and not used on the Models II, 12, 16, & 6000.

The unique features of the Model II, Model 12, Model 16, Model 6000, and overlapping with the Models 4/4P/4D, are the allocation of memory in 32KB blocks (upper & lower memory); single boot ROM select line for all except the Models 4 & 4D; the relocation of the keyboard and video memory to the higher end of memory, with separate decoding/selection lines; the Model 4 memory map selection line; and the higher 4.04Mhz speed of the Z80A.

Firstly, the 32KB memory blocks made all of memory accessible WITHOUT a programmatic slowdown for any memory, so programs can default to running at full speed.

Secondly, boot ROMs are selectively shadowed (turned on/off) on the Model II, Model 4P, Model 12, Model 16, & Model 6000, independent of the memory map selected. Model III/4 BASIC ROMs in the Model 4 & Model 4D are automatically shadowed by selection of a Model 4 memory map, and will never be addressed in Model 4 Mode. But if they are shadowed-in on the other models, a slowdown selection is necessary. This line is called ROMCE* for the 4KB boot ROM in the Model 4P. The Model II version is split in half for the two 2KB boot ROMs called ROM0CE* & ROM1CE*, but we'll use ROMCE* because the second boot ROM was never installed on the Model II. This signal is provided to the interface via one probe clip on the cable.

Thirdly, input from the keyboard matrix is not hardwired into the bus, but it is shadowed in & out; it is only accessible when the KEYB* signal is active (shadowed in). This signal is provided to the interface via another probe clip on this cable.

Fourthly, access to the the 2KB video RAM for the 80-character x 24-line screen is not hardwired into the bus, but it, too, is shadowed in & out; it is only accessible when the VID* signal is active (shadowed in). This signal is provided to the interface via an additional probe clip on the cable.

Fifthly, this mode is enabled only when pulled up by SEL1 when the Model II/4 Mode cable being plugged in; it is pulled low to indicate Model I/III mode when this cable is disconnected. SEL1 selects a Model 4 Mode memory map on the motherboard, or is tied to a Vcc pull-up on J1 for Models II/12/16/6000. This is a single line with a probe clip on the cable.

Sixthly, the Ground could always use equalization, so there is a another Ground wire with a probe clip on the cable.

Finally, the Model II series can run at full (4Mhz) or half (2Mhz) speed, jumper selectable, while the Model 4 series can run at full or half speed, software selectable.This can be reported to the interface through the FAST signal. If this line is pulled high, the slow, native TRS-80 bus clock will be 4Mhz, and the Turbo fast speed will be 16/20Mhz with 1 Wait State. If this line is pulled low, the slow, native TRS-80 bus clock will be 2Mhz (or 1.774Mz), and the Turbo fast speed will be 16/20Mhz with 3 Wait States. This can be tied to the Model 4 FAST signal, the Model II Clock Speed jumper, or pulled-up via an exposed pullup pin on J1. This is the last probe clip on this cable.

This cable is attached to the interface (J3) with a 6-pin Dupont connector: ROMCE*, KEYB*, VID*, SEL1, Ground (equalization), & FAST, with the 6 probe-clips on the other end of the cable. This is for all TRS-80s Models II, 4, 4P, 4D, 12, 16, & 6000, only; this Model II/4 Mode cable is removed & not used for the Model I or III TRS-80s.

That defines the signal interface to the TRS-80. What remains is the Z80 signal passthrough between the Turbo Z80 board and the TRS-80 Z80 socket, and the power & ground rails.