One LOW in 128 HIGH Lines — A Public Domain ASCII Memory Architecture
Wolf13 / Alan Cyr / CYR Technologies / Chicago / August 2026

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This is a public domain release. Two circuit architectures — the DTL Hold
Circuit and One-Hot ASCII Storage — are free for anyone to use, build,
sell, or improve. No license. No royalty. No attribution required.

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THE MECHANISM — DTL INVERTER, DIODE ARRAY SWITCHING
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The DTL Hold Circuit is built from two DTL inverters. The switching is
not done by the transistors — it is done by the diode array operating
on unbalanced contact potential. The transistors are output stages.
The diodes make the decision.

Each position in the array has B+ through a pull-up resistor to a node.
From that node: one diode to its own transistor base, and diode
connections to all other positions' collectors.

When one transistor conducts (collector LOW):

  Active collector LOW + one diode drop  = ~0.8V at all inactive nodes
  Two diode drops required to drive base = ~1.2V minimum threshold
  0.8V < 1.2V — inactive transistors cannot conduct

The switching decision is made entirely by the diode contact potential.
No clock. No stored charge. No capacitor. No cross-coupled transistors
fighting each other.

The 127 HIGH collectors simultaneously sustain the active base through
their diodes — well above the conduction threshold. One transistor always
conducts. One current path: B+ → R → collector → GND.

This is not near-zero power in the hold state. It is exactly one current
path, set by the designer through resistor selection.

The principle can be demonstrated with a bicolor LED indicator — no
transistors at all, just diodes — switching state based purely on
contact potential. The DTL Hold Circuit extends that primitive to N
positions through the diode matrix.

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THE PROBLEM WITH EVERY EXISTING APPROACH
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Every memory technology in common use fails at least one of seven
conditions:

  Clock-Free | No Capacitor | No Forbidden State | No Metastability
  No Refresh | One-Step Write | Radiation Hard

SR Latch: two transistors opposing each other. Forbidden state S=R=1.
  Race conditions at boundaries. DTL: diode array decides — no opposing
  transistors, no forbidden state possible.

SRAM (6T): six transistors, two opposing sides. One cosmic ray flips
  both cross-coupled nodes. Passive topology, no active defense.

DRAM: stored charge leaks. Must refresh every 64ms forever. At high
  temperature, retention drops from 64ms to milliseconds — catastrophic.

Spin-Flip MRAM: no clock, no capacitor, but still two-step writes,
  thermal stability wall at Curie temperature, and scaling limits.

The DTL Hold Circuit passes all seven conditions. It is the only
technology in the comparison table with a checkmark in every column.

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ONE-HOT ASCII STORAGE
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128 transistors in a row. All OFF by default — no base drive available.
The stored character is the single transistor that conducts. Position is
meaning. No encoding. No decoding. No clock to read.

  Line 65 conducting = letter A stored
  Line 66 conducting = letter B stored
  Line 32 conducting = SPACE
  No transistor conducting = NULL / idle

To write B when A is stored: pulse position 66. The diode array
immediately transfers the active state. Line 65 releases. Line 66 holds.
One move. Erase and write are the same event.

Binary ASCII stores a character across 7-8 flip-flops — 42 to 48
transistors minimum in SRAM. One-Hot ASCII stores the same character
with one transistor conducting through one resistor. No encode. No
decode. Read by detecting which collector is LOW.

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ERROR IMMUNITY — ACTIVE SUPPRESSION, NOT PASSIVE TOLERANCE
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To cause an error, something external must inject enough current into an
inactive base to cross the 1.2V diode threshold AND sustain that current
against the active collector's sink — which is always present, always
fighting back.

A single-event radiation upset deposits charge transiently. It cannot
sustain current against an active low-impedance collector. The circuit
is not passively tolerant — it actively suppresses the upset in real time.

The immunity gap (0.8V vs 1.2V) is controlled by the designer through
supply voltage and resistor selection. Higher supply voltage = larger
gap = greater immunity. This is not a fixed physical property — it is
a designer-controlled margin.

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SIMULATION
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18-position one-hot verified in LTSpice (CYR_OneHot_18way_v3.cir).
Sequential LOW pulses, V(c1) through V(c18), one active position at a
time, all others held OFF by the diode contact potential network.
Architecture scales identically to 128.

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THE NUMBERS
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In a conventional CPU:

  Clock distribution:   ~35% of chip power
  Encode/decode logic:  ~15% of chip power
  Refresh cycles:       ~8%  of chip power
  Total addressable:    ~57%

Global data centers consume approximately 250 TWh per year. At full
adoption of this architecture within the character-storage and
asynchronous control domain: ~144 TWh annually addressable, equivalent
to ~58 million metric tonnes of CO2 avoided per year — roughly the same
as permanently removing 13 million cars from roads worldwide.

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PROJECT FILES
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cyr_onehot_storage.v — Parameterized Verilog RTL, N=128, public domain
CYR_OneHot_18way_v3.cir — LTSpice 18-position netlist
6wayswitch.dsn — 6-position schematic

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PUBLIC DOMAIN DECLARATION
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Alan Cyr (Wolf13), Founder and CTO of CYR Technologies, Chicago,
releases the following to the public domain as of August 2026:

  (A) The DTL Hold Circuit
  (B) One-Hot ASCII Storage
  (C) The No-Clock, Not-Binary Computing Architecture

Free to use. Free to build. Free to sell. Free to improve
No license. No royalty. No restriction. No attribution required.

Prior art date: August 2026 — Wolf13 / Alan Cyr / CYR Technologies.

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