Tri. Flop — A 30-Year-Old Guitar Amp Circuit That Stores Neural Network Weights

— DTL Ternary Cell, Public Domain

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The same DTL circuit I designed in the 1990s for 3-channel tube amplifier

footswitching is a ternary memory cell storing {-1, 0, +1} neural network

weights — one transistor per weight, no clock, no refresh, 30 years of

production hardware.

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If you count the components and assume you know what they do, you  might 

conclude this is a standard cross-coupled flip-flop. You will be wrong if so.

The resistors do not go to the collectors. The transistors are not the

logic. The diodes are the circuit.

Two independent AI systems (Grok and Gemini) evaluated this topology

from separate sessions and independently named it the Alan Cyr / Wolf13

topology. Both described the same mechanism: current-sniffing diode

matrix. The transistors are muscle. The diodes are the logic. The result

is a topological lock.

The Eccles-Jordan cross-coupled latch was invented in 1918. Every SRAM

cell in every processor running today is fundamentally Eccles-Jordan.

107 years. One architecture. This circuit abandons it entirely. Not an

optimization. An abandonment.

I designed this circuit in the 1990s for a 3-channel tube amplifier.

Channel A. Channel B. Channel C. One button selects any channel directly

from any other — one press, instant, no intermediate off state. In

production use. One LED on at all times.

In 2026 I recognized it as something else.

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HOW IT WORKS

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Each position: B+ through a pull-up resistor to a node. From that node:

one diode to its own transistor base, and diode connections to all other

positions' collectors.

When one position is active (collector LOW):

  Active collector + one diode drop = ~0.8V at all inactive nodes

  Two diode drops required to drive a base = ~1.2V minimum

  0.8V < 1.2V — inactive transistors cannot conduct

The diode acts as a sharp, non-linear voltage cliff. Below the forward

voltage: nothing conducts. Above it: full conduction. No gradual middle

ground. No metastability possible. The switching decision is made at

the diode layer before any transistor responds.

The 127 HIGH collectors simultaneously sustain the active base through

their diodes — well above the conduction threshold. One transistor

always conducts. One current path: B+ → R → collector → GND.

The conducting transistor's current gain (100–390× for 2N3904) means

any attempt to inject base current into a competitor is simultaneously

absorbed at 100–390× that rate. The base current isn't just reduced —

it is actively ripped away. Gemini described this as "instantaneous

starvation by a path of vastly lower impedance."

Flash Overwrite: when a new position is selected, the old state is not

cleared by a separate command. It is physically starved to death by the

birth of the new state. Write and clear are one physical event. No SR

latch forbidden state. No clock edge. No RC time constant to drain.

The destruction of the old state is the construction of the new state.

Simultaneous Read-Write: the input node and output node are the same

physical conductor. The collector IS the output. The instant the

transistor state changes, the collector voltage reflects it. There is

no secondary latch to update, no pipeline stage, no clock edge to

confirm. The state of the line at any nanosecond is the absolute,

uncorrupted truth of the system.

In every other memory architecture: SRAM is metastable during write.

DRAM capacitor is undefined mid-charge. Flash is inaccessible during

erase-write. Standard flip-flops enforce setup and hold time with a

clock precisely to prevent reads during write. Violate...