4R4C - FPGA Radio Challenge

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There are many ways to build a radio. I have made many radios. Todays life is going more and more digital so are the radio designs. But can we build a radio with 4 resistors and 4 capacitors? If we add one magic component called FPGA, then we can. But FPGA's are digital? Components (For the Radio RX function):

4 Resistors
4 Capacitors
1 FPGA (any Xilinx 7 series FPGA will do)

This is all we need to implement a radio receiver with frequency coverage over 500MHz.

Do you think this can not be done? Think again.
Do you think you have solved he challenge? Submit the solution to: ( challenge * trenz.biz )

Prize for the first challenger will be ...

To be continued...

Components

4 × Resistor

4 × Capacitor

1 × FPGA

Project Logs

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First proto setup
Antti Lukats • 04/06/2017 at 17:51 • 2 comments

This is the first lab setup I made. The R+C are on the backside of the blue proto PCB
Yes the same setup was tested with 500Mhz signal as well..
And 500MHz tested as well..
Antti Lukats • 03/30/2017 at 14:53 • 2 comments

When I posted the challenge, assuming that the circuit works at frequencies 500 + MHz.
But I had not tested it.
Now I have, this is 500MHz signal received with the same 4R+4C lab setup I used for first tests at 3.5MHz.
SNR is not good, actually its really really bad, but hey this is hand soldered prototyp on prototyping board, and the 500MHz frequency is pretty hard to some dirty circuit soldered on generic protoboard. Also the R and C values are not at all optimal, I did not change them, as I only wanted to see proof of concept that it works.
So basically the same circuit can receiver from below 1MHz to 500+ MHz.
Almost solved, stage #1
Antti Lukats • 03/29/2017 at 06:39 • 0 comments

The Challenge went online at Xilinx.com also today
Challenge xilinx.com
There is already a solution close enough to get accepted for the UltraFast category. Close enough but not the same as my solution. But no more hints at this point.
So lets the Challenge to continue, so other have some chance too.
3.51MHz and 200 microvolt, we have signal!
Antti Lukats • 03/28/2017 at 14:55 • 0 comments

After I figured out that this may actually work I could not hold back any more. Some of the resistors I found where 0402 size but they are still easy to solder on plain normal perforated prototype board. A few hours later I did see the radio signal received and converted to digital inside the FPGA.
This is how 200 mV signal at 3.510MHz feed into FPGA using 4R4C Radio Receiver Circuit looks like.
Ok and here we have signal at 200 microvolt. I had to build an attenuator to get signal level down.

View all 4 project logs

Build Instructions

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Step 1

Step 1: Solve the challenge.

Step 2: Solder those 4 resistors and 4 capacitors to build the radio receiver on any piece of prototype board.

Step 3: Connect your 4R4C radio circuit to proper FPGA and proper pins.

Step 4: Design your Radio using Xilinx Vivado.

Step 5: Test it!

Discussions

Antti Lukats wrote 03/29/2017 at 06:26

keep going! I am now more confident the challenge solution comes soon. And please look again at the sketch I made, this is really all you need. Add wires and net labels. Nothing more.

Are you sure? yes | no

Mike Butts wrote 03/29/2017 at 00:42

An OBUFT (tri-state output driver) can act as a pass transistor to ground. Use 4 OBUFTs on FPGA pins A, B, C, D. Set all Inputs I to 0, and drive each input T with one of four clocks from an MMCM, all at the receive frequency, with phase shifts of 0, 90, 180, 270 degrees.

Let's call the resistors R1-R4 and caps C1-C4. 1) Connect one end of R1, R2, R3 and R4 to the antenna. 2) Connect the other end of R1 to C1, R2 to C2, R3 to C3, R4 to C4. 3) Connect the other end of C1 to pin A, C2 to B, C3 to C, C4 to D. 4) Connect the R1-C1 wire to XADC A +, R3-C3 to XADC A -, R2-C2 to XADC B +, R4-C4 to XADC B -.

C1 can be charged by the antenna when the 0 degree clock is low, connecting pin A to ground. When A's clock is high C1 cannot charge because it's open circuit. C1 connects to the + side of an ADC. The clock driving C is 180 degrees out of phase, so C3 is on the - side of that ADC, which is the I (in-phase) output. Clocks driving B and D are 90 degrees out of phase, on the other ADC, which is the Q (quadrature) output.

Process I and Q in the FPGA to demodulate the received signal. For example, a good AM demod is the magnitude of the I,Q vector: sqrt(I*I+Q*Q). Drive audio output with a PWM FPGA output pin.

The only problem left is tuning the clocks to receive at any frequency. MMCM has lots of choices but not every possible frequency. But then you just said frequency range, not all frequencies ;-).

If you drive the MMCM with a tunable clock generator like the Si5351, controlled by a MicroBlaze on the FPGA, then you'd have a proper radio. (https://learn.adafruit.com/adafruit-si5351-clock-generator-breakout/overview) Si5351 has three independent outputs, use one to clock the FPGA logic and another for the radio MMCM's clock. The FPGA needs some sort of oscillator so the Si5351 doesn't even increase the part count.

Are you sure? yes | no

Yann Guidon / YGDES wrote 03/29/2017 at 00:56

Wow.

I supposed that there would be IOs involved, in output mode or something.

"An OBUFT (tri-state output driver) can act as a pass transistor to ground." That's sure, but the pass is to 0V. I mentally connected the IO pin to the capacitor to the wrong pin, since I supposed that the other capacitor pin was connected to 0V.

So I stopped there.

I'm going to sleep now, and I feel I learned something :-D

Are you sure? yes | no

Mike Butts wrote 03/29/2017 at 01:19

Thanks!

Are you sure? yes | no

Yann Guidon / YGDES wrote 03/29/2017 at 01:03

There is a problem with your system : bias.

Since the tristate buffer switches to 0V, and you get AC in (capacitively coupled), you end up with negative voltages at the ADC inputs.

You need at least a preamp that adds some bias, or else you can't put an antenna (or you lose 1/2 of the signal)

Are you sure? yes | no

Yann Guidon / YGDES wrote 03/29/2017 at 01:07

Oh I may have misunderstood Mike's idea, I look again at the "incomplete" diagram and I "get" it now :-D

Are you sure? yes | no

Yann Guidon / YGDES wrote 03/29/2017 at 01:24

did I get it right ?

It seems to be reversed, compared to Mike's description, but this could solve the bias issue and it just follows your "hints", I didn't move any part and it sort of makes sense...

Are you sure? yes | no

Yann Guidon / YGDES wrote 03/29/2017 at 01:33

The bias is not solved though, so it might be a simple trick of switching once to 0V, the next time to +Vcc, but that's ugly and would radiate like crazy on the antena...

So maybe the tribuff actually switches to Vcore or something like that (around 1V) and the ADC accepts a wider range of voltages, like 3.3V ?

Are you sure? yes | no

Antti Lukats wrote 04/07/2017 at 05:13

to be CORRECT, yes to be REAL, no, for some reason the XADC inputs do self bias. This is not in the datasheet.

Are you sure? yes | no

Mike Butts wrote 03/28/2017 at 20:45

Ah, I'd forgotten, 7-series has an XADC block, a pair of 12-bit 1Msps ADCs, just what you need for I and Q. Now how to do a commutating mixer without four pass transistors?

Are you sure? yes | no

Yann Guidon / YGDES wrote 03/28/2017 at 21:37

The contest speaks about a 500MHz radio receiver, which is out of the 1MSP (1MHz with I/Q) range. So maybe a mixer is needed ? Is there a ring modulator or something, driven by a PLL output ?

Are you sure? yes | no

Mike Butts wrote 03/28/2017 at 22:37

You commutate the mixer at the receive frequency. Then the ADCs capture the bandwidth around the receive frequency. This is a common technique in software-defined ham radios: http://www.wparc.us/presentations/SDR-2-19-2013/Tayloe_mixer_x3a.pdf . Question is, how to switch the weak antenna signal with an FPGA...

Are you sure? yes | no

Mike Butts wrote 03/28/2017 at 20:34

It's a commutating mixer, right? 4 RC networks, 90 degrees apart, feeding I and Q ADCs. But how do you get a pair of ADCs?

Are you sure? yes | no

4R4C - FPGA Radio Challenge

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Components

Project Logs

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First proto setup

And 500MHz tested as well..

Almost solved, stage #1

3.51MHz and 200 microvolt, we have signal!

Build Instructions

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Discussions

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4R4C - FPGA Radio Challenge

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