I've got a potential design for the v2 prototype. I just want to get some confirmation from Microchip that I've selected the correct chip. The schematic is in the files.

Since the XMega core runs at 3.3 volts, we can do away with the logic level translation stuff we had on the v1 prototype. It has an internal 32 MHz oscillator and separate clocking for USB, so we don't need to connect a crystal. Since the 3.3 volt supply has to drive everything, we'll upgrade from an LDO to a PAM2305 buck converter. So the incoming USB power simply goes straight into the two switching supplies - the HV supply for the entropy generator and the 3.3 volt logic supply.

I've confirmed that my compiler supports the 32A4U, and that I have PDI support in avrdude. I do have to select and get (or make) a PDI programmer of some sort. I've got a pile of 32u2s, so I could make an AVR mkII clone - there are a few out there that use LUFA based firmware and are open.

After basic functionality is working, one thing I hope to try to explore is using the USART in SPI master mode and remapping it to the SPI pins. The reason for this is that the USART is double-buffered, which would potentially eliminate the inter-byte gaps and increase performance. We'll see how that works out eventually, I hope. I still think prospects for initial performance of ~300 kB/sec are good. I may, however, be able to reduce the inter-byte gaps during transfers by being careful about ordering operations. If I perform the SPI write immediately after the SPI read and then prepare for the next operation before waiting for the SPI operation to finish, I can use the time while the hardware is shifting bits out profitably. With that, the inter-byte gaps might not be so bad. Given that the bulk read/write operations have to have an XOR operation for the crypto in the middle, it's already a job the DMA engine can't really help with.