At the outset, I had hoped that I would be able to switch to using USART0 in SPI master mode by setting the SPI and USART0 bits in the port C REMAP register. The USART0 bit shifts USART0 from bits 0-3 to bits 4-7, which realign it with the SPI bits. But it turns out that the SPI bit swaps the MOSI and XCK pins on the SPI device so that it matches the USART layout, not vice versa.

Lame.

So the only way to even try the USART in SPI master mode is to swap the two pins on the board and actually remap the SPI device to match the USART layout, and then try USART in SPI mode by undoing that remap and shifting USART0 up to the top 4 bits of the port.

I'm going to have to spin some new boards and give that a try. I do think the double buffering that the USART in SPI master mode can do is going to be worth the effort.

Meanwhile, with interrupt-driven AES and ordinary SPI the current board is getting just shy of 200 kB/sec, which is actually usable. If I can just work out some SCSI behavior issues with the card removal, I'll be able to put the current version up for sale.