VDP character cell address masking feature

A project log for TMS9900 compatible CPU core in VHDL

Retro challenge 2017/04 project to create a TMS9900 compatible CPU core. Again in a month... Failure could be an option...

erik-piehlErik Piehl 11/01/2017 at 21:200 Comments

I pushed to GitHub an update to my TMS9918 VHDL core, adding support for undocumented but somewhat widely used and known graphics mode 2 masking features. The lack of this feature was the culprit of making the megademo (see my previous update) not working properly in quite a few screens in a systematic way.

With these fixes the megademo works much better, but there are still some problems (including the fact that the demo gets stuck at a certain point after running successfully through quite a few demo phases - the CPU core continues to run, but it appears to be in some kind of a loop that it cannot escape). So as always, fixing some bugs means its time to fix the next bugs...

The character masking feature appears in two places in the VHDL code, using low bits of registers 4 and 3 as character cell masks, the example below illustrates the use of register 4 during character cell address calculation in graphics mode 2:

-- Graphics mode 2. 768 unique characters are possible.
-- Implement UNDOCUMENTED FEATURE: bits 1 and 0 of reg4 act as bit
masks for the two
-- MSBs of the 10 bit char code. This allows character set to be limited even in this mode.
vram_out_addr <= reg4(2) -- MSB of the address
    & (char_addr(9 downto 8) and reg4(1 downto 0))  -- Character code with masks for bits 9 and 8
    & char_code & ypos(2 downto 0); -- 8 bit code and line in character