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16bit RISC Processor

A 16bit single cycle RISC processor suporting R format I format BEQ and JMP format.

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Instruction memory processes 16bit instructions.
R format is supported with ADD, Subtract, Increment, Decrement, OR, NAND, XOR, NOT.
I format is supported with Load Word, Store Word
Branch instructions followed by BEQ (Branch by x lines if both registers are equal)
Jump instruction(Jumps to the provided instruction number)
There are still 2 opcode ports yet to be used and will be updated soon.
The software used was Xilinx and speed went upto 119.89 MHz.

You can visit- http://verilogcodingandlearning.blogspot.in/2017/04/16bit-risc-processor.html

Maximum frequency attained till date-

Multiplexers - 178.348 Mhz

Register File - 598.498 Mhz

Data Memory- 274.72 Mhz

Datapath- 112.215 Mhz

Top Module- 119.97 Mhz

Fetching and Executing instruction each take single clock cycle.

Fetching cycles had AluOp as XXXX and result too as XXXX

The next cycle is the result of the fetched instruction and Reg-write or memory write is procesed at the fall of the clock cycle.

Register R0 always contains zero although it can be changed and overwritten by any instruction. However it isn't suggested. MIPS procesors have R0 set as zero. The Mux with input from Register and sign extend also has an input zero incase R0 is overwritten and one needs to use. Hence its select line in of 2 bits.

Patch_1.0.0.v

Patch 1.0.0 What has been added- 1. JIZ instruction Jump to referred address if Register Location has zero as content. opcode- 1111 Intruction- 1111_(4bit Register)_8bit address

v - 14.01 kB - 04/02/2017 at 21:44

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Program Counter.v

Program Counter which counts and iterates over addresses of instructions

v - 285.00 bytes - 04/01/2017 at 18:56

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Risc Top Module.v

This describes the topmost module which connects datapath and control unit

v - 473.00 bytes - 04/01/2017 at 18:26

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datapath RISC-1.jpg

All the connections between modules. Note- It shows datapath connection and not control unit

JPEG Image - 127.34 kB - 04/01/2017 at 18:26

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SignExtend.v

It used to extend 4 bits from instruction [3:0] to 8 bits for jump or branch offset and for ALU

v - 147.00 bytes - 04/01/2017 at 18:26

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View all 12 files

  • 1 × Xilinx Simulator

View all 3 project logs

  • 1
    Step 1

    First the instructions- Each instruction is of 16 bits that means [15:0]. Further dividing it

    we select opcode- [15:12] then rest [11:0] bits depend on the instructions.

    For R type we have

    ADD [--R1--] [--R2--] [--R3--] Each Register here is of 4 bits.

    So number at location of R1 added to number at location of R2 will be stored at address pointing to R3 register.

    SUB [--R1--] [--R2--] [--R3--]

    Similarly we have for subtract too.

    Ex- 0001 0001 0010 0111

    it means 0001 for SUB opcode 0001 is address of R1 0010 is address of R2 and 0111 is address of destination R3

  • 2
    Step 2

    Now for I format we have Load Word and Store Word

    LOAD [--R1--] [--R2--] [--sign extend--]

    now number stored at R1 will be added to sign extend and the result will be an address pointing to a location in RAM. the data from RAM is then stored in R2

    Ex- 1011 0100 0111 1010

    Sign extend of 1010 is 11111010 added to data at location 0100 and result will be stored at location 0100 in Register

    STORE [--R1--] [--R2--] [--sign extend--]

    ex 1100 0100 0111 1010

    Sign extend of 1010 is 11111010 is added to content of 0100 and we get an address of RAM. Then the content of 0111 is stored in that address of RAM.

  • 3
    Step 3

    Branch format- I have included only one branch function.

    Its BEQ (Branch if equal)

    Ex 1101 0010 0100 0111 if the contents of 0010 and 0100 are same then Z flag wil be triggered and with that PC wil increment by 1 which will be added to 0111 a.k.a 3 in decimal. This will be the amount of instructions by which PC will jump.

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