Programming the YGREC

A project log for YGREC-РЭС15-bis

YG's 16bits Relay Electric Computer, rebooted

Yann Guidon / YGDES 04/14/2017 at 09:170 Comments

So far the instruction format and datapath are well defined and it's time to think about the programming paradigms used by the YGREC.

The architecture does every important thing (as far as I'm concerned) and I notice that it has no opcode.

That's a bit unusual though it's reminiscent of the "Move Machine" ou "Transfert Triggered Architecture". Where the TTA/MM starts operation when operands are available and there are only 2 register addresses, the YGREC has 3 addresses and the operation is immediate.

How should instructions be written ? There are two schools : the algebraic form (used by ADi DSPs) and the direct form (mapping the hardware fields). I like the ADi style (ah, the memories of the SHARC and ADSP2105)

R1 = D1 or T1 SHR (IFZ)
but it's more coherent to stick to the representation of the hardware assembler board...
T1 SHR or D1 => R1  (IFZ)

That's where I see that I should swap the ALU field and the SRCX field on the assember board. Too laaaaate... But I can move the ADD/ROP2 button. You will not notice much.

There, I fixed this :

The disassembly board must also be swapped :

So there, you have everything clearly laid out, just write the code and enter each column in order, and you have your instruction in binary !

Almost in the same vein, there is another question : how to encode NOP ?

Starting with the #YASEP Yet Another Small Embedded Processor I set the following convention:

NOP does nothing so it should be encoded in a way that does not modify the state of any register. Let's see how each field is affected :

In the end, NOP is equivalent to

R1 PASS R1 => R1

INV however requires a sort of reset of the program. This corresponds to hitting a place in EEPROM that has not been programmed and reads 0xFFFFFF.

INV is now equivalent to

And the new register map is: