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YGREC-ECL

At the opposite site of the spectrum, this project is incredibly smaller and faster than the relay implementation of YGREC.

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I try to implement the YGREC architecture with another discrete method, this time using tiny and incredibly fast transistors. Only ECL can keep pace with the BFS480, a dual-NPN packaged in tiny SOT323-6 with a GBW product of 7GHz.

I've been musing with ECL for the germanium version of YGREC, then pseudo-ECL with silicon, but here it's the real deal ! The gate density is significantly better and I hope I'll overcome the difficulties that Dieter Müller encountered with the BFR93A, 10 years ago...

Some time ago, like, 10 years ago, Dieter Müller worked on http://6502.org/users/dieter/decl/decl1.htm for his next discrete computer and he had to shelf the idea. I have the pretention to do better :-P

Why ?

  • Because I have a viable computer architecture (the YGREC, as described in #AMBAP: A Modest Bitslice Architecture Proposal and #YGREC-РЭС15-bis) so the ISA and structure are well understood and out of the way. As long as I got MUX, I can build it.
  • I also have new laboratory equipment that would help. It's good to be able to inject 4× 200MHz signals and watch them on a 500MHz scope :-)
  • Because I have Dieter's log to examine and take lessons from !
  • And my new secret weapon : the BFS480... two 7GHz GBW transistors in a single, tiny SOT323-6 package (aka SC70), a 10× increase in density (I'm not even taking double-sided PCB into account because I don't feel like doing 4-layers PBC, we'll see if I'll be compelled)

Of course it will be hard but I have already solved many issues with the relay implementation. Dieter's log correctly warns about signal distribution across the whole processor, but I counter with this:

  • smaller transistors means smaller circuits and shorter traces. The SC70 package is very low profile so the bitplanes can be stacked much closer to each other, 5mm apart instead of 25mm apart with the relays. This greatly shrinks the backplane ! That's less than 10cm for the distribution backbone, or roughly 300ps.
  • I have thoroughly analysed the fanout, partition and distribution of the main control signals of the YGREC so they are under control. Instead of spending my time playing with a few ECL gates to make them run faster, I'll focus on the distribution networks, where all the speed is actually lost. I can cut corners with the logic gates, sacrificing a bit of raw speed for a low power consumption and fewer transistors (which again, just like in ASIC design, is a virtuous circle)

I just hope that I'll have enough parts...


Logs:
1. A sidequest, already

.

  • 5400 × BFS480 dual NPN, 7GHz BGW, 8V, 8mA,

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Morning.Star wrote 04/08/2017 at 22:49 point

Lol :-)

And 200MHz, thats a disgustingly fast rig Yann, well done.

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Yann Guidon / YGDES wrote 04/08/2017 at 22:57 point

Thank you eBay ;-)

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