I have been waiting a long time but they're here now so I'm happy.
I was feeling inspired by @Yann Guidon / YGDES's project #YGREC16 - YG's 16bits Relay Electric Computer and it's DRAM, so I got the same relays that his project uses. Since I'm in California these Russian relays feel much more exotic to me... And I like different languages than English/Spanish that I don't see so often, so the Russian, French, and English all on the same box seemed really cool to me.
Anyways, I decided to do some tests and make a bread boarded prototype. For this one I have a video.
After running further tests I discovered that the RAM worked well. So I decided to make all the RAM I could manage: 3 bytes using 24 capacitors and 3 relays (1 relay per byte).
A few tests of this board confirmed that it works. Beautiful!
I am working on some better ways to place the capacitors. I want to get to at least 512 bytes per 100 cm2. Oh, and that's enough for a bootable drive >:D. Could this one day be plugged into a PC and booted from? Just a thought....
Yea. Now I need to REALLY increase density. I'm already thinking SMD + OSH park.
I only have maybe 60 diodes. Some are in PCBs. So, I would have to order a few hundred diodes from @Digi-Key Electronics. I don't want to spend more money on parts other than maybe more capacitors, so I decided to run a simulation of the DRAM without diodes. It worked! and it's still non-volatile in it's weird capacitor-based way.
I don't have many relays (yet), that's why I didn't actually build the circuit. It does seem in the simulation however that the diodes make the memory work worse, not better. A real circuit will tell if I need the diodes.
I think the diodes were for preventing capacitor loops. Since I am using relays to 'disable/enable' the capacitors, the loops never occur. So in theory the diodes are unneeded.
I have been looking at DRAM for a while. I first saw how it worked on an example circuit for this circuit simulator. I had an idea then that a semi-volatile memory could be invented. It would be like DRAM in that it uses capacitors but like EEPROM in that it would remember the data through a power cycle. I wasn't thinking about relays then, so I was having troubles with not having any energy leak too fast. Essentially this strange semi-volatile memory would only remember for a time, say, a few minutes at best. And would still need a refresh.
I happen to have some relays coming in the mail, so I thought about this idea. I think I could use relays or a mix of relays and logic chips to prevent leakage. The multiplexer and data lines would be a mix of relays and logic chips so that when power is lost no capacitor has a lead connected into the rest of the circuit. The circuit would be broken. Of course, the charge of the capacitor would die over time anyways, but it would be semi-volatile. Once powered on again the capacitors would be reconnected.
Basically I want to make semi-volatile DRAM. Kinda weird but really cool!
I came up with some schematics and ideas during dinner tonight. They include the design I already tried, a hypothetical design, and another design that for some reason doesn't work.
The schematic to the top left is a tested and working design, but is horribly inefficient as far as chip usage goes. Im looking for better designs (More about that in a moment). The one below it is practically guaranteed to work. The one to the right, for some weird reason, does not work. I used 4Mhz because it was easy just lying around.
So basically I need mass capacitor storage. Like what Yann Guidon / YGDES suggested. He suggested that I use capacitors + 2 diodes to - what it looks to me like - "address" the capacitors and write/read to the ones that are selected. I have been messing around with this but haven't had any success. Bummer because it would actually be cool to use this kind of DRAM in my #SBP-CPU (Slice Based Processor) project. I'm going to keep trying though so hopefully I can solve it and mass store data in capacitors. Sweet!
My current working design uses a buffer gate for each bit of data. A capacitor connects to the input of the buffer. A diode goes from the output of an AND gate to the capacitor, positive lead to the AND. The AND's inputs connect to the output of the bit's buffer gate and to the refresh clock. For the buffer I used 2 NOT gates, which works well. Im going to create an array of maybe 4 bytes for test. Here is an image of what I have so far: