The heart of this design is the VLSI VS23S010D-L chip. It is a 1 Megabit SPI SRAM with Serial and Parallel Interfaces and Integrated Video Display Controller, which outputs a composite video signal.
Possible video resolutions, PAL and NTSC modes might be exclusive depending on the mouted crystal (4.433618MHz or 3.579545MHz):
The chip has a 3.3V interface, so a level shifter logic is required, which is done by a 74LVC4245A buffer, which is able to handle SPI Mbps speed better that a simple FET based level shifter. A footprint for a 512Kbit EEPROM for bitmaps and character memory is added, but is probably too slow for effective operation. On a suggestion of [kbdhog] the current version does have a 2Mbit SPI FLASH chip for better speed and memory size. Now I am dreaming of SPI DMA, which just gave me an idea of a small PLD and a parallel flash memory to implement that.
The circuit on the bottom left of the rev1 schematic is used to fill the 10cm x 10cm PCB space and left to the reader to figure out its functionality. ;-) I will end up with ~780 copies of this circuit which will last a lifetime or they might show up on Tindie.
Rev3 of the board (with added SPI FLASH) is being designed, might be the final one if things go well. Writing SW is so hard in comparison. Currently NTSC 320x200 and PAL 300x240 resolutions are working with the color bar test image. Both resolutions have 8bit color depth.