I decided I'm going to need to simulate this thing first. So I have to get a simulator. I haven't written VHDL in a few years, but it used to be my career focus. So I'm downloading Xilinx Vivado Webpack. I haven't used this before, but I was proficient with Xilinx ISE.
I'd like to have instructions take one clock cycle, but I'm not sure if I can pull that off. I'd also like to have one shared memory. But if I want to fetch instructions and write back to the memory in one clock cycle, then I'll need a dual-port. I don't think I can find a friendly one for breadboarding. So I think I'm stuck with either separate instruction/data memories, or multiple clock cycles per instruction. The timing problems make me uncomfortable enough that I will need to simulate.
I'm also still split on 8-bit memory bus or 16-bit memory bus. If I want to fetch an instruction in one cycle, I need a 16-bit memory bus (two parallel 8-bit chips). I could do two cycle fetch with an 8-bit bus from sequential memory locations, and then one cycle execute, but that'll just slow down execution and take more control resources. So I still have decisions to make on my architecture.