So from the system design doc you can see a few important details:
First off the stand-alone circuitry for the quadrature clock generation remains from the softrock. I had thought about using the BBB to do it however there were multiple people online that have complained about doing it that way. I think one of the issues is that the BBB digital IOs were designed nicely to interface with digital logic, however the quad-clk-gen is clocking what is essentially an analog circuit. Things like noise and uniform phase are important here. So since it's a fairly proven design and there are not too many complaints about it I think it will be fine to keep it.
The other point to make is with the devices used for the muxing and QSD; the FST3253. Doing a fairly large search through all of the muxes I could find was unproductive; it seems that there aren't too many devices out there that do a better job than this part. I dislike that it's 5V only, but that's not a big deal. M0RZF noted that there may be a better alternative in the TS3A5017 so I'll have to compare and make a choice between the two. Otherwise they are both pretty similar.
Along this vein there is a whole lot of research here:
But to be honest it's a lot to look through so I think I'll just design in an I/Q 'squarer' as recommended by M0RZF. In this case it's just a buffer that will minimize phase disturbances in the QSD. That is, it will cause the QSD to switch in the same points in the rising edge of the clock every time. Makes sense conceptually, but I'm not a pro at this stuff :)