04/11/2019 at 17:06 •
For some months ago I began to program in python to try to make a compiler for my CPU, and after many days and hours in trying to make it, I am finally done, I've made a simple compiler which is somewhat equivalent to assembly (mind You I've never made something like that before, and it was quite hard to begin, but got done in the end), then I made a relatively higher level compiler which can create a for loop in the first compilers language.
I made a simple nested for loop where to check if any number from 2 to 9 is prime, and after compiling the program, I got the results:
2 is prime,
3 is a prime,
4 is not a prime,
5 is prime,
6 is not a prime,
7 is prime,
8 is not prime and
9 is not prime
01/22/2018 at 11:11 •
I'm working on making a CISC CPU ( it's gonna be an Alpha CPU ) which has implemented custom functions with build-in parameter stacks and up to 256 stacks of each functions and up to 256 different functions.
I've also read a relative short introduction on assembler and learned a way more effective way to set up the registers to both split them into ALU registers and general purpose registers ( which I should have thought of before )
08/05/2017 at 15:05 •
The new Schön Core Delta v.0.3.0 ALU is going to get brand new functions since the new versions have 5 bit dedicated to different functions as well as the Control Unit which includes a small FPGA that I designed ( which is probably really inefficient and small compared to 'modern' FPGA's ), multiplication ( physical computing ), division ( physical computing ) and 1 bit logic ( which uses ffffffff as true and aaaaaaaa as false )
I am also going to use CLA Adders to both add and subtract ( probably also Mul and Div ) to make it way faster than the ripple version ( since it's 32 bit it'd take tremendous amounts of time to compute with ripple adders )
I really hope to make the new ALU way more flexible than the previous versions and also faster but as a consequence way bigger since it has to have a FPGA, CLA Adder, physical Mul, Div etc.
07/18/2017 at 18:29 •
Schön Core 1.Generation Delta v.0.3.0 has a whole new type instruction set ( all the other types except Lite versions have 4 bits dedicated for functions ). Its function bits is now 5 bits ( mostly because the ALU needs that many for all the necessary functions ) and is going to be able to handle screens with the dimensions up to 4294967296 by 4294967296 pixels ( the previous was able to handle 64 by 32 pixels ) and have the ability to control opacity and colour for each pixel ( previous was only on or off ) and since it's 32 bit it also have the space for 8 bit opacity. Not only the ability for better images but it is also going to get better inter computer controls ( as you may have noticed I really focus on inter computer connection efficiency because I think it is the way forwards in technology )
07/14/2017 at 18:28 •
I've found some problems with the way I made 'the old' SP-DF system and have found some solutions to it making it way more user-friendly and easy to use compared to the old versions.
'The old' SP-DF, I realized, would not be able to communicate with other units/computers fast enough nor did it not have enough settings to easily send small to large amounts of data quick if necessary.
'The new' version has a setting for controlling in more detail whether to fetch from native memory or external memory/devices and a setting for sending data or receive data only but fetch as from native memory.
I even plan to create a ( as far as I've seen myself ) new kind of digital receiver that can receive more bits than the bit width by having two RAM blocks running at full speed to respectively storing from the input then sending to the main RAM ( I'm only 15 and don't know lots about electric engineering etc. so don't blame me if I'm wrong )
05/10/2017 at 08:06 •
The Schön Performance Drive Fetch ( SP-DF is used to more effective external drive fetching ) has been implemented in the Delta v.0.2.5 and I plan to implement it Alpha, Beta and Lite versions