USB device stack:
Micah Dowty wrote the pure polling USB code which I changed into interrupt + polling using 3-4 of TI App notes and use header file from libusb for the data structure. I strip off most of TI's callback functions that are hard to understand. The resulting code works kind of like V-USB and work well under SDCC.

USB_JTAG:
The hight level code came from ixo.de : http://ixo-jtag.sourceforge.net/#usb_jtag
usb_jtag project that uses Cypress FX2 which is a modern day 48MHz 8051 chip. The code was nicely optimized and with machine code for the 8051. I changed the low level GPIO bit banging code and grafted the high level code on to my USB stack. 

USB Blaster:
The USB_JTAG code there was ported over to Microchip on this Japanese page: http://sa89a.net/mp.cgi/ele/ub.htm for making the Altera USB Blaster clone.

I ported the EEPROM code and USB descriptor code which are critical for cloning Altera USB Blaster back.

Hardware:

TUSB3410 connection - bus powered

Power supply and EEPROM (not actually used)

Level Translation:

Level Translation:

VIO is the I/O voltage of the target.  It comes in via series resistor R20 to power the level translation circuits.  Q5 is a shunt regulator.  It clamps down the I/O rail to limit the voltage to about 3.4V if you connect VIO to say a 5V system.  

Note: U1 has an absolute maximum suply voltage of 6.5V, it is only spec for up to 3.6V for normal operation.

For the signals going out of PCB, it passes through U1 which acts as a level translator.   If my target operates on 1.8V, U1 would be on a 1.8V power supply and its output would be between 0V to 1.8V.  The 74LVC series is great for that as its logic input can exceed the power supply voltage.  There are series terminating resistors on the output to reduce signal reflection as the dingle is usually connected to a target using loose wires.

Note: 74LVC part is very fast and they require terminating resistors if your track is longer than about 0.5 inches!

Now what about the extra bits of transistors circuits?

Q4 (in Cascode topology) is a level translation circuit that convert the incoming TDO back to 3.3V for the TUSB3410.  The capacitor C7 is for compensating for Miller capacitance that would otherwise slow down the circuit.

Q2 & Q3 forms a bidirectional level translation for the TMS/SDWIO.  (SWDIO and SWDCLK are for ARM debugging not needed for USB Blaster Clone)

Jim Hagerman wrote a paper "Two Transistors Form Bidirectional Level Translator"

www.hagtech.com/pdf/translator.pdf

" Tests show  that the circuit operates easily up to 300kHz. The major impediment to fast operation is the delay that occurs when Q1 comes out of saturation on a rising edge."

I played around with the circuit in LTSpice and figured out how to improve the performance by adding a couple of capacitors that speeds up the discharging of the Miller capacitance that caused the slow down.  

(My LTSpice circuit on left)

LTSpice plot: Blue: 1.8V input, Green: 3.3V output.

I played with the pull up values to improve the rise time. Notice that the delay is gone as the capacitor C1 discharged the Miller capacitance.  By the way, my simulation is for 10MHz!

This is how it looks like translating from 3.3V down to 1.8V

How is this useful vs the usual ones built with MOSFET circulating on the Internet?  

e.g. 2N7002 has Vgs threshold of:  0.8V (min), 2.1V (typ) and 3V (max).

You'll have a bit of trouble using that part with that wide spread of a range of a threshold  for level translation.  The BJT transistors have a input threshold of around 0.7V with a much smaller spread, so it can easily work down to 1.x volt range and not limited for 3.3V.  I/O voltages are going down these days and 3.3V is only the first stop.

This is just here to show that discrete bidirectional level translation can be done using discrete parts that I have lying around.   For any logic translation, I would not recommend this circuit as...

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