Project Logs

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• First SoC Processor Chosen: Intel Z3770 "Bay Trail T"

  Emparete LLC • 08/19/2014 at 14:33 • 0 comments

  August 19, 2014

  Intel Z3770 "Bay Trail T" SoC is made for tablets. Quad 64-bit cores, up to 2.39 GHz with Turbo-Boost. Comes in a 1380 pin BGA package. Mouser.com has them available in single quantities for around $50.

  Z3770 General Info, Data Sheet Vol 1, Vol 2

  This SoC will require blind and buried vias to layout the PCB. Will need to use another PCB software for the SoC module layout, as Designspark cannot do blind and buried vias, and has a limitation of 1000 pins per component.

  Intel has a Reference Tablet Design for OEMs using this SoC, but requires signing a Non-Disclosure Agreement to get it. As the SoC module is intended to be Open Hardware, I will not seek to obtain this reference design or look at it if I have the chance, so I can freely publish the complete schematics and the PCB files of this module.

• FPGA to DDR3 nets trace length Matching

  Emparete LLC • 08/17/2014 at 21:32 • 0 comments

  August 17, 2014

  Spreadsheet of trace length match tolerances and actual lengths for the FPGA to DDR3 nets posted:

• Work in progress FPGA module design files posted

  Emparete LLC • 08/13/2014 at 16:56 • 0 comments

  August 13, 2014

  Posted Designspark PCB files at Designspark Design Share site:

  Project, Schematic, PCB

• FPGA and DDR3 layout

  Emparete LLC • 08/09/2014 at 14:51 • 0 comments

  August 9, 2014

  Last 6 days worked on a 4-layer PCB layout of the FPGA module. FPGA selected in this first module is Xilinx Spartan-6 in a 324-pin BGA package. This is the same package used in the Novena laptop, and comes in 4 different capacities. PCB software used is Designspark. 

  Designspark is surprisingly feature-rich for a free (not open-source) schematic and PCB software. It is very intuitive to use, and has no artificial limits in size, pin count, or number of layers. I tried Eagle but did not like its unintuitive UI. Open source KiCAD is lacking some features that I need, such as split power planes.

  Schematic and PCB layout for the FPGA connecting to a DDR3 DRAM is being worked on first.

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