08/13/2014 at 01:20 •
I purchased a couple of 8x8 LED matrices. The LEDs are controlled by a MAX7219 chip with a SPI interface. In the video below you can see the results. I chained two matrices together to form a 8 x 16 grid. The vertical direction represents the download rate for a one seconds. The scale is roughly adjusted such that a full vertical bar corresponds to the maximum download rate on my network. I plan on getting another set of LED matrices of a different color to display the upload rates.
I designed a front plate and back plate and had them laser cut out of 3mm clear acrylic. I didn't have any standoffs on hand, so I made some out of cut down pens and zip ties.
08/13/2014 at 01:19 •
With v1.1 populated, I was able to interface with the MAC+PHY chip via the parallel interface and begin sending download rate data over the serial port. I wrote a Python program to plot the data, and compared it with the bandwidth graphs provided by DD-WRT on the router. To my delight, the plots track pretty closely.
08/13/2014 at 01:18 •
I began searching for a microprocessor with a parallel interface with sufficient data rates for my needs. I found the PIC24F to be a suitable candidate and began laying out a pcb to interface with ENC624J600 breakout board I purchased.
PCB v1.0 back from fab
PCB v1.1 back from fab
PCB v1.2 back from fab
08/13/2014 at 01:16 •
I created a prototype passive network tap out of female RJ-45 push down sockets. Under normal conditions, data is transmitted on TX and recieved on RX, however when sniffing traffic on a line, the listening device must treat each direction as seperate receive channels. To handle two RX channels, two NICs are required.
10/100Base-T Passive Network Tap
I ran into Mike Ossman at a GNU Radio conference and received one of his Throwing Star LAN Tap. He uses them as business cards, how cool is that? If I ever get around to populating the board, it will certainly clean up my protyping efforts a bit.
MAC + PHY chip
The bandwidth meter operates at the ethernet frame level, counting bytes transmitted and received (including headers). As such, I looked for a MAC + PHY chip with a large receive buffer and the ability to handle raw ethernet frames. I first looked at the
WIZnet module, but found it's raw ethernet support lacking. The interface could only store one raw ethernet frame at a time and block any incoming packets until the first frame is read. For this application, the blocked packets would lead to an incorrect byte count and defeat the purpose of the meter.
I ultimately selected the ENC624J600 chip.
Unlike the WIZnet module, the ENC624J600 does not have a built in TCP/IP stack, but had a much better raw ethernet interface. I ordered a single
Olimex breakout module from Mouser to get going. I planned on making a PCB with two ENC624J600 chips and some flavor of Atmel to keep track of the packet count and drive the display. The SPI IO pins on the ENC624J600 are 5v tolerant and the Atmega128 recognized ~3.3v as high, so the level shifters weren't needed.