As usually happens, I was thinking about some aspect of this design when I had a blinding glimpse of the obvious. It is going to cause me to toss the first version of the LTC4041 design without even populating the PCBs.

Simplifying the input switches:

The first version of the design had two pairs of FET switches to disconnect the input source. I got to thinking that I did not need to actually disconnect it since it just presents a high resistance load when the AC power fails. I could use a single FET switch if I connected the drain to the input and the source to the VIN pin of the LTC4041. This reverses the body diode of the FET so that the input won't hold up the output voltage to the load if the input power returns. But in this configuration the body diode of the input FET won't let the input voltage fall more than a diode drop below the output voltage. In this application this is not a problem -- as long as the input voltage is less than the 4.75V power fail comparator threshold of the LTC4041. 

Here's the version 2 schematic:

M1 is a 30V, 4mΩ RDSon, logic level FET that I used on one of the magnetic switch projects. The package is a 3.3x3.3mm DFL powerPak, which has become pretty standard for these types of devices. I also upgraded C4 to a 150µF low-ESR tantalum (Vishay 594D157X9010D2T -- 10V, D-case, 80mΩ ESR). There are a few of these in my inventory and I haven't been able to use it because of its size, but in this case it fit.

The Layout is Smaller:

1.05"x1.613" Almost 15% smaller than the first version. I don't particularly like the way that the output and input traces spiral around each other, but that was forced by the pinout of the LTC4041. 

So now I will order another set of PCBs. Three of these boards should cost about $8.50 from OSH Park. It will take 3-4 weeks to get them.